Revision History
1189
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
Revision History
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from October 27, 2016 to March 14, 2018
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Page
•
Changed all instances of "bootstrap loader" to "bootloader" throughout document
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•
Added the list item "A security violation (access of protected areas in flash such as protected BSL)" as an event that
generates a BOR in
System Reset and Initialization
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•
Added the note "The high-side SVS must be enabled for software to modify the RTC and LFXT registers" in
High-Side Supervisor (SVS
H
) and High-Side Monitor (SVM
H
)
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•
Updated the description of the AUXKEY and LOCKAUX bits in
,
Start-up
.....................................
•
Updated
,
Software Flow Chart
, to clear LOCKAUX before configuring registers
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•
Updated the description of the AUXKEY bit field in
,
AUXCTL0 Register Description
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•
Updated description in
,
Flash Memory Segmentation
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•
Added the NOTE that begins "To synchronize TD0 and TD1..." in
TDxCTL0 Register
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•
Added the NOTE that begins "The TDHMx bits of master and slave..." in
,
TDxHCTL0 Register
.........
•
Added the NOTE that begins "The TDHMx bit of the slave timer must be equal to..." in
TDxHCTL1
Register
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•
Corrected (changed from 0h to undefined) the reset value for the AE bit in
,
RTCAMIN Register –
Calendar Mode With BCD Format
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•
Corrected the reset value of the AE bit in
,
RTCAMIN Register Description
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•
Added the note that starts "The ADC10SC bit is automatically cleared..." in
,
Pulse Sample Mode
....
•
Changed the description of SD24BPREx operation in the first paragraph in
,
Conversion Operation Using
Preload
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•
Updated list of devices that support the trigger generator in the note in
Trigger Generator
.............
•
Updated list of devices that support the trigger generator in the note in
,
SD24BTRGCTL Register
......
•
Updated list of devices that support the trigger generator in the note in
SD24BTRGOSR Register
...
•
Updated list of devices that support the trigger generator in the note in
SD24BTRGPRE Register
....
•
Added the note "Reliable reception of IrDA signals" in
,
IrDA Decoding
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•
Added information about clearing flags in
,
UART State Change Interrupt Flags
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•
Corrected "UCBxI2COA0 = 0x0412;" in
Slave RX With 7-Bit Address
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•
Corrected the description of the UCRXIFG3 bit in
,
UCBxIFG Register Description
..........................
•
Changed bit 12 to a standard Reserved bit and consolidated contiguous Reserved bits in
USBPLLCTL
Register Description
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