0h
Timer_D: TDR
(max)
(Timer_D: TD2CMB = 1,
TECXFLTEN2=0,
TECEXCLREN=1)
TECXFLTEN1=1,
Timer_D: TDCL0
Timer_D: TDCL2
Timer_D: OUT2
TECEXCLR
TECXFLT1
Output Mode 3: Set/Reset
EQU2
Timer_D: TDCL1
EQU1
EQU0
EQU2
EQU1
EQU2
EQU1
EQU2
0h
Timer_D: TDR
(max)
Output Mode 8: Reset/Set
(Timer_D: TD2CMB = 0,
TECXFLTEN2=1,
TECEXCLREN=1)
Timer_D: TDCL0
Timer_D: TDCL2
Timer_D: OUT2
TECEXCLR
TECXFLT2
Ton
Toff
Toff
Toff
Ton
Ton
Ton
Ton
Ton
TEC Operation
550
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
Timer Event Control (TEC)
20.2.3.1 External Input Events Affect Timer Output
shows how the external signals affect the Timer_D output in a Power Factor Corrector (PFC)
application.
Figure 20-2. External Input Events Affect Timer_D Output
shows an example in which channels are combined.
Figure 20-3. Timer_D Output With Channel Combination
20.2.4 Module Level Connection Between TEC and Timer_D
The TEC and Timer_D modules are connected through internal signals.
shows the
interconnection between TEC and Timer_D module. See the
for more Timer_D module
information.