RTC_C Registers
645
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
Real-Time Clock C (RTC_C)
24.4.4 RTCCTL3 Register
Real-Time Clock Control 3 Register
(1)
This bit is implemented in only the F677xA, F673xA, and F672xA devices. For other devices, this bit is reserved and always reads as 0.
(2)
These bits are not reset on POR; they are reset based on a signal derived from the AUXVCC3 supply voltage level.
Figure 24-7. RTCCTL3 Register
7
6
5
4
3
2
1
0
Reserved
RTCLOCK
(1)
RTCCALFx
(2)
r0
r0
r0
r0
r0
rw-[0]
rw-(0)
rw-(0)
(1)
This bit is implemented in only the F677xA, F673xA, and F672xA devices. For other devices, this bit is reserved and always reads as 0.
Table 24-8. RTCCTL3 Register Description
Bit
Field
Type
Reset
Description
7-3
Reserved
R
0h
Reserved. Always reads as 0.
2
RTCLOCK
(1)
RW
0h
Real-time clock lock. When this bit is set, all control in LPM3.5 retention is held
and not accessible even when the device is under BOR.
0b = LPM3.5 retention logic unlocked
1b = LPM3.5 retention logic locked
1-0
RTCCALFx
RW
0h
Real-time clock calibration frequency. Selects frequency output to RTCCLK pin
for calibration measurement. The corresponding port must be configured for the
peripheral module function. The RTCCLK is not available in counter mode and
remains low, and the RTCCALF bits are don't care.
00b = No frequency output to RTCCLK pin
01b = 512 Hz
10b = 256 Hz
11b = 1 Hz
24.4.5 RTCOCAL Register
Real-Time Clock Offset Calibration Register
(1)
These bits are not reset on POR; they are reset based on a signal derived from the AUXVCC3 supply voltage level.
Figure 24-8. RTCOCAL Register
15
14
13
12
11
10
9
8
RTCOCALS
(1)
Reserved
rw-(0)
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
0
RTCOCALx
(1)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
Table 24-9. RTCOCAL Register Description
Bit
Field
Type
Reset
Description
15
RTCOCALS
RW
0h
Real-time clock offset error calibration sign. This bit decides the sign of offset
error calibration.
0b = Down calibration. Frequency adjusted down.
1b = Up calibration. Frequency adjusted up.
14-8
Reserved
R
0h
Reserved. Always reads as 0.
7-0
RTCOCALx
RW
0h
Real-time clock offset error calibration. Each LSB represents approximately
+1 ppm (RTCOCALS = 1) or –1 ppm (RTCOCALS = 0) adjustment in frequency.
Maximum effective calibration value is ±240 ppm. Excess values written above
±240 ppm are ignored by hardware.