eUSCI_A UART Registers
1054
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode
39.4.12 UCAxIV Register
eUSCI_Ax Interrupt Vector Register
Figure 39-23. UCAxIV Register
15
14
13
12
11
10
9
8
UCIVx
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
0
UCIVx
r0
r0
r0
r0
r-(0)
r-(0)
r-(0)
r0
Table 39-19. UCAxIV Register Description
Bit
Field
Type
Reset
Description
15-0
UCIVx
R
0h
eUSCI_A interrupt vector value
00h = No interrupt pending
02h = Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt
Priority: Highest
04h = Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG
06h = Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG
08h = Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG;
Interrupt Priority: Lowest