RTC_A Registers
591
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
Real-Time Clock (RTC_A)
22.3.31 RTCPS0CTL Register
Real-Time Clock Prescale Timer 0 Control Register
Figure 22-32. RTCPS0CTL Register
15
14
13
12
11
10
9
8
Reserved
RT0SSEL
RT0PSDIV
Reserved
RT0PSHOLD
rw-0
rw-0
rw-0
rw-0
rw-0
r0
r0
rw-1
7
6
5
4
3
2
1
0
Reserved
RT0IP
RT0PSIE
RT0PSIFG
r0
r0
r0
rw-0
rw-0
rw-0
rw-0
rw-(0)
Table 22-32. RTCPS0CTL Register Description
Bit
Field
Type
Reset
Description
15
Reserved
R
0h
Reserved. Always reads as 0.
14
RT0SSEL
RW
0h
Prescale timer 0 clock source select. Selects clock input source to the RT0PS
counter. In real-time clock calendar mode, these bits are do not care. RT0PS
clock input is automatically set to the output of RT0PS.
0b = ACLK
1b = SMCLK
13-11
RT0PSDIV
RW
0h
Prescale timer 0 clock divide. These bits control the divide ratio of the RT0PS
counter. In real-time clock calendar mode, these bits are don't care for RT0PS
and RT1PS. RT0PS clock output is automatically set to /256. RT1PS clock
output is automatically set to /128.
00b = Divide by 2
01b = Divide by 4
10b = Divide by 8
11b = Divide by 16
00b = Divide by 32
01b = Divide by 64
10b = Divide by 128
11b = Divide by 256
10-9
Reserved
R
0h
Reserved. Always reads as 0.
8
RT0PSHOLD
RW
1h
Prescale timer 0 hold. In real-time clock calendar mode, this bit is don't care.
RT0PS is stopped via the RTCHOLD bit.
0b = RT0PS operational
1b = RT0PS held
7-5
Reserved
R
0h
Reserved. Always reads as 0.
4-2
RT0IP
RW
0h
Prescale timer 0 interrupt interval
00b = Divide by 2
01b = Divide by 4
10b = Divide by 8
11b = Divide by 16
00b = Divide by 32
01b = Divide by 64
10b = Divide by 128
11b = Divide by 256
1
RT0PSIE
RW
0h
Prescale timer 0 interrupt enable
0b = Interrupt not enabled
1b = Interrupt enabled
0
RT0PSIFG
RW
0h
Prescale timer 0 interrupt flag
0b = No time event occurred
1b = Time event occurred