DAC12_0
DAC12_0OUT
2.5 V, 2.0 V, or 1.5 V reference from REF module
DAC12SREFx
V
R−
V
R+
DAC12_0DAT
DAC12_0Latch
DAC12_1
DAC12LSELx
V
R−
V
R+
DAC12_1DAT
DAC12_1Latch
TB2
TA1
DAC12DF
DAC12RES
AV
SS
00
01
10
1 1
00
01
10
1 1
00
01
10
1 1
Latch Bypass
DAC12LSELx
TB2
TA1
00
01
10
1 1
00
01
10
1 1
Latch Bypass
To other modules
DAC12_1DAT Updated
DAC12_0DAT Updated
1
0
0
1
ENC
0
1
ENC
DAC12GRP
1
0
DAC12GRP
DAC12SREFx
AV
SS
00
01
10
1 1
DAC12_1OUT
DAC12AMPx
3
Group
Load
Logic
DAC12AMPx
3
AV
CC
AV
CC
DAC12DFJ
DAC12DF
DAC12RES
DAC12DFJ
DAC12_0CALDAT
DAC12_1CALDAT
x2, x3
DAC12OG
x2, x3
DAC12OG
DAC12IR
/2, /3
DAC12OG
DAC12IR
/2, /3
DAC12OG
V
eREF+
(devices with CTSD16 this signal is V
/V
)
REFBG
eREF+
V
REF+
Copyright © 2017, Texas Instruments Incorporated
DAC12_A Introduction
824
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
DAC12_A
Figure 31-1. DAC12_A Block Diagram for a Device With Two Modules