UCS Operation
164
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
Unified Clock System (UCS)
On many devices, the XT1 pins are shared with general-purpose I/O ports (refer to the device-specific
data sheet for availability). At power up, the default operation is XT1, LF mode of operation. However, for
devices that have XT1 shared with general-purpose I/O ports, XT1 will remain disabled until the ports
shared with XT1 are configured for XT1 operation. The configuration of the shared I/O is determined by
the PxSEL bit associated with XIN and the XT1BYPASS bit. Setting the PxSEL bit causes the XIN and
XOUT ports to be configured for XT1 operation. If XT1BYPASS is also set, XT1 is configured for bypass
mode of operation, and the oscillator associated with XT1 is powered down. In bypass mode of operation,
XIN can accept an external clock input signal and XOUT is configured as a general-purpose I/O. The
PxSEL bit associated with XOUT is a don't care. If the PxSEL bit associated with XIN is cleared, both XIN
and XOUT ports are configured as general-purpose I/Os, and XT1 is disabled.
On devices that do not share XT1 with general-purpose I/O ports, XT1 is enabled at power up. In bypass
mode of operation (XT1BYPASS = 1), XIN can accept an external clock input signal, and XT1 is powered
down.
XT1 is enabled under any of the following conditions:
•
XT1 is a source for ACLK (SELA = {0}) and in active mode (AM) through LPM3 (OSCOFF = 0)
•
XT1 is a source for MCLK (SELM = {0}) and in active mode (AM) (CPUOFF = 0)
•
XT1 is a source for SMCLK (SELS = {0}) and in active mode (AM) through LPM1 (SMCLKOFF = 0)
•
XT1 is a source for FLLREFCLK (SELREF = {0}) and the DCO is a source for ACLK (SELA = {3,4})
and in active mode (AM) through LPM3 (OSCOFF = 0)
•
XT1 is a source for FLLREFCLK (SELREF = {0}) and the DCO is a source for MCLK (SELM = {3,4})
and in active mode (AM) (CPUOFF = 0)
•
XT1 is a source for FLLREFCLK (SELREF = {0}) and the DCO is a source for SMCLK (SELS = {3,4})
and in active mode (AM) through LPM1 (SMCLKOFF = 0)
•
XT1OFF = 0. XT1 enabled in active mode (AM) through LPM4. For devices that support LPMx.5, XT1
also remains enabled.
NOTE:
XT1 enable for MSP430F543x, MSP430F541x devices
XT1 is enabled under any of the following conditions:
•
XT1 is a source for ACLK, MCLK, or SMCLK (SELA = {0}), MCLK (SELM = {0}),
or SMCLK (SELS = {0}) and in active mode (AM) through LPM3 (OSCOFF = 0)
•
XT1 is a source for FLLREFCLK (SELREF = {0}) and the DCO is a source for
ACLK, MCLK, or SMCLK (SELA = {3,4}), MCLK (SELM = {3,4}), or SMCLK
(SELS = {3,4}) and in active mode (AM) through LPM3 (OSCOFF = 0)
•
XT1OFF = 0. XT1 enabled in active mode (AM) through LPM4.
5.2.5 XT2 Oscillator
Some devices have a second crystal oscillator, XT2. XT2 sources XT2CLK, and its characteristics are
identical to XT1 in HF mode. The XT2DRIVE bits select the frequency range of operation of XT2.
XT2 may be used with external clock signals on the XT2IN pin by setting XT2BYPASS. When used with
an external signal, the external frequency must meet the data sheet parameters for XT2. XT2 is powered
down when used in bypass mode.
Some devices support XT2 bypass operation with external clock inputs on a different external supply
domain, called DV
IO
. Refer to the device-specific data sheet. On these devices, DV
IO
has a voltage range
of 1.8 V ±10%. When using the XT2 bypass operation with external clock inputs on DV
IO
, it is required that
XT2BYPASSLV = 1. For example, when XT2BYPASSLV = 1, it is assumed the external clock signal
swings from 0 V to DV
IO
. With XT2BYPASS = 0, it is assumed the external clock signal swings from 0 V to
DV
CC
. The use of XT2BYPASSLV allows for interfacing to external clock sources that reside on either the
DV
CC
or DV
IO
supply domains. When used with an external signal, the external frequency must meet the
data sheet parameters for the chosen mode. XT2 is powered down when used in bypass mode.