USCI_A SPI Mode Registers
982
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
Universal Serial Communication Interface – SPI Mode
37.4.7 UCAxRXBUF Register
USCI_Ax Receive Buffer Register
Figure 37-11. UCAxRXBUF Register
7
6
5
4
3
2
1
0
UCRXBUFx
r
r
r
r
r
r
r
r
Table 37-9. UCAxRXBUF Register Description
Bit
Field
Type
Reset
Description
7-0
UCRXBUFx
R
undefined
The receive-data buffer is user accessible and contains the last received
character from the receive shift register. Reading UCRXBUF resets the receive-
error bits and UCRXIFG. In 7-bit data mode, UCRXBUF is LSB justified and the
MSB is always reset.
37.4.8 UCAxTXBUF Register
USCI_Ax Transmit Buffer Register
Figure 37-12. UCAxTXBUF Register
7
6
5
4
3
2
1
0
UCTXBUFx
rw
rw
rw
rw
rw
rw
rw
rw
Table 37-10. UCAxTXBUF Register Description
Bit
Field
Type
Reset
Description
7-0
UCTXBUFx
RW
undefined
The transmit data buffer is user accessible and holds the data waiting to be
moved into the transmit shift register and transmitted. Writing to the transmit
data buffer clears UCTXIFG. The MSB of UCAxTXBUF is not used for 7-bit data
and is reset.