Instruction Set Description
333
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
CPUX
6.6.4.4
CLRA
* CLRA
Clear 20-bit destination register
Syntax
CLRA Rdst
Operation
0
→
Rdst
Emulation
MOVA #0,Rdst
Description
The destination register is cleared.
Status Bits
Status bits are not affected.
Example
The 20-bit value in R10 is cleared.
CLRA
R10
; 0 -> R10