MSP430 and MSP430X Instructions
226
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
CPUX
6.5.2.7
MSP430X Instruction Execution
The number of CPU clock cycles required for an MSP430X instruction depends on the instruction format
and the addressing modes used, not the instruction itself. The number of clock cycles refers to MCLK.
6.5.2.7.1 MSP430X Format II (Single-Operand) Instruction Cycles and Lengths
lists the length and the CPU cycles for all addressing modes of the MSP430X extended single-
operand instructions.
(1)
Add one cycle when Rn = SP
Table 6-17. MSP430X Format II Instruction Cycles and Length
Instruction
Execution Cycles, Length of Instruction (Words)
Rn
@Rn
@Rn+
#N
X(Rn)
EDE
&EDE
RRAM
n, 1
–
–
–
–
–
–
RRCM
n, 1
–
–
–
–
–
–
RRUM
n, 1
–
–
–
–
–
–
RLAM
n, 1
–
–
–
–
–
–
PUSHM
2+n, 1
–
–
–
–
–
–
PUSHM.A
2+2n, 1
–
–
–
–
–
–
POPM
2+n, 1
–
–
–
–
–
–
POPM.A
2+2n, 1
–
–
–
–
–
–
CALLA
5, 1
6, 1
6, 1
5, 2
5
(1)
, 2
7, 2
7, 2
RRAX(.B)
1+n, 2
4, 2
4, 2
–
5, 3
5, 3
5, 3
RRAX.A
1+n, 2
6, 2
6, 2
–
7, 3
7, 3
7, 3
RRCX(.B)
1+n, 2
4, 2
4, 2
–
5, 3
5, 3
5, 3
RRCX.A
1+n, 2
6, 2
6, 2
–
7, 3
7, 3
7, 3
PUSHX(.B)
4, 2
4, 2
4, 2
4, 3
5
(1)
, 3
5, 3
5, 3
PUSHX.A
5, 2
6, 2
6, 2
5, 3
7
(1)
, 3
7, 3
7, 3
POPX(.B)
3, 2
–
–
–
5, 3
5, 3
5, 3
POPX.A
4, 2
–
–
–
7, 3
7, 3
7, 3