BOR shadow
brownout circuit
PMMRSTIFG
RST/NMI
SYSNMI
s
s
PMMBORIFG
PMMSWBOR event
s
Delay
BOR
SVSHIFG
PMMPORIFG
PMMSWPOR event
s
from SVS
H
s
SVSHPE
SVMHVLRIFG
from SVM
H
s
SVMHVLRPE
SVSLIFG
from SVS
L
s
SVSLPE
SVMHLVLRIFG
from SVM
L
s
SVMLVLRPE
Delay
POR
WDTIFG
Watchdog Timer
s
EN
from port
wakeup logic
s
PUC Logic
Module
PUCs
…
.
MCLK
notRST
Delay
clr
clr
clr
System Reset and Initialization
56
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
System Resets, Interrupts, and Operating Modes, System Control Module
(SYS)
Figure 1-1. BOR/POR/PUC Reset Circuit