Tektronix Socket 7 TMS109A, Instruction Manual

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TMS 109A Socket 7 Microprocessor Support
4–1
Maintenance
This chapter contains information on the following topics:
H
Probe adapter circuit description
H
How to replace a fuse
Probe Adapter Circuit Description
The active components on the probe adapter are: five GAL 22V10D PALs for
signal synthesis, one LM3940ISX for 5 V to 3.3 V conversion, and one
PPL-Buffer and one PLL (phase locked loop) low-skew clock generator for clock
distribution with buffer.
The PALs implement three sequential state machines that monitor the Socket 7
microprocessor bus and generate three important signals:
H
PIPED_D indicates Socket 7 microprocessor bus pipelining is occurring
H
LAST_D indicates the end of a Socket 7 microprocessor bus cycle
H
DVALID_D indicates valid data is present on the Socket 7 microprocessor
data bus
These signals are required for the Clocking State Machine (CSM) of the logic
analyzer to accurately strobe addresses and data information from the Socket 7
microprocessor bus.
The CSM is tightly linked to the processor bus T-states and is synchronized to the
Socket 7 microprocessor on a clock by clock basis. It is possible that unpredict-
able bus behavior by an alternate bus master may cause the bus tracking
machines to lose track of the bus. If this occurs, the bus tracking mechanism will
automatically re-synchronize and reset itself when the Socket 7 microprocessor
exits bus back off or bus hold.
If resynchronizing and reseting the bus tracking machines is not adequate,
jumper J920 will disable the bus tracking PALs during any alternate bus master
(HLDA) cycle or back off (BOFF #) cycle. If you disable the bus tracking PALs,
acquisition of back off or hold cycles are inhibited, and one sample containing
unusable information is recorded to show a cycle occurred.
A 20-pin connector, Intel In-Target Probe (ITP), is located on the probe adapter.
Your system under test has system reset circuitry that can not be accessed
through the SPGA socket, but you may connect the DBRESET signal (or the
active low, open collector version OC_DBRESET*) to your system reset
circuitry externally.