Tektronix Socket 7 TMS109A, Instruction Manual

Page: 70 / 113

Acquiring and Viewing Disassembled Data
2–24
TMS 109A Socket 7 Microprocessor Support
not taken, flushed the speculative prefetch cycles, and started fetching at
0x38988 (sample 750), which contained the next instruction after the JNE.
Sample Address Data Mnemonic Control
--------------------------------------------------------------------------------
00038986 B575C90F JNE 0003893D (32) P_FETCH
734 000207D8 00000008 ( MEM READ ) P_MEM_RD
736 000207E8 00000046 ( MEM READ ) P_MEM_RD
738 00038988 000000BA ( FLUSH ) P_FETCH
0003898C 24558900 ( FLUSH ) P_FETCH
740 00038990 20C2619D ( FLUSH ) P_FETCH
00038994 6FBF6D00 ( FLUSH ) P_FETCH
742 00038998 CDBFDE6F ( FLUSH ) P_FETCH
0003899C FFEFFFF7 ( FLUSH ) P_FETCH
744 000389A0 FFFFEDAE ( FLUSH ) P_FETCH
000389A4 F6FFF7EF ( FLUSH ) P_FETCH
746 00038938 DB9BFF33 ( FLUSH ) P_FETCH
0003893C 0002A3E3 ( FLUSH ) P_FETCH
748 00038940 6D8A0000 ( FLUSH ) P_FETCH
00038944 204D8A10 ( FLUSH ) P_FETCH
750 00038988 000000BA MOV EDX,#00000000 (32) P_FETCH
0003898D 24558900 MOV 24[EBP],EDX (32) P_FETCH
Figure 2–10: Speculative Prefetch cycles
NOTE
. The microprocessor also has a Branch Target Buffer and often performs
speculative prefetching of branch target addresses (no matter if they are taken or
are not taken). The disassembler usually interprets the correct flow of execution
but cannot do so deterministically.
Cache Invalidation cycles are needed to keep the microprocessor cache contents
consistent with external memory. On a nonburst cycle that is also a Cache
Invalidation cycle, the data and address will be valid as probed. On a burst cycle
that is also a Cache Invalidation cycle, the data will be valid, but the addresses
will not be valid as probed and the software will try to calculate the address from
the surrounding cycles. Fetch cycles are disassembled. A letter
c
to the left of the
mnemonic indicates a Cache Invalidation cycle, where the AHOLD signal was
active.
On all burst cycles, only the first cycle contains a valid address. The Socket 7
microprocessor does not increment the address for a burst. The disassembler
calculates the remaining burst cycle addresses for display.
The Socket 7 microprocessor provides a special mode called System Manage-
ment Mode where the Socket 7 microprocessor CPU executes code from a
Cache Invalidation Cycles
Burst Cycles
System Management
Mode (SMM)