Tektronix Socket 7 TMS109A, Instruction Manual

Page: 20 / 113

Getting Started
1–4
TMS 109A Socket 7 Microprocessor Support
Configuring the Probe Adapter
There are five jumpers on the probe adapter. Table 1–1 lists the jumper positions
and functions.
Table 1–1: Jumper positions and function
Probe adapter Position Function
J240
MFG_TEST 1–2
OPEN
When the processor extends the clock speed to below 40 MHz, the jumpered pins 1-2
turn the phased lock loop into a buffer that disables the phased lock loop signal.
Default, phased look loop signal enabled
J250
CLK 1–2
2–3
Extends the Socket 7 microprocessor system speed between 40–150 MHz
Extends the Socket 7 microprocessor system speed between 20–75 MHz
J900
Proc Sel 1–2
2–3
Supports microprocessors that do not have the D/P# pin.
Supports microprocessors that have the D/P# pin.
J910
D/P# 1–2
OPEN
Acquires the D/P# signal from pin AE35 of the socket being probed.
Acquires the D/P# signal from an external source. If this jumper is left open, you must
route the D/P# signal to pin 1 of this jumper from an external source. This allows you to
probe your system from the Dual socket as long as the D/P# signal is accessible on the
system board. Ensure that the jumper J900 is in position 2–3 before routing the D/P#
signal to pin 1 of J910.
J920
Tracking 1–2
2–3
Enables tracking of burst and pipelined cycles while BOFF# and HLDA are asserted
Disables tracking of burst and pipelined cycles while BOFF# and HLDA are asserted.
This setting can be used if an external master’s signal timing is different from that of the
P54C.
J921
SYNTH 1–2
2–3
Enable Address Synthesis (A(2:0) are derived from BE(7:0)#)
Disable Address Synthesis (A(2:0)=0)
To acquire data at frequencies below 40 MHz on the probe adapter, short the two
pins on J240. This disables the phased lock loop signal to all clocked compo-
nents. Figure 1–1 shows the location of J240 on the probe adapter.
MFG_TEST Jumper