Tektronix Socket 7 TMS109A, Instruction Manual

Page: 48 / 113

Setting Up the Support
2–2
TMS 109A Socket 7 Microprocessor Support
Figure 2–1 shows two typical bus cycles: a single cycle transfer followed by a
burst transfer. The ADS#, Address and Data signal forms are delayed by two
CLK cycles. This diagram also shows the timing relationships of LAST_D and
DVALID_D, the signals synthesized by sequential logic in the PALs.
Sample point 1
A31-A0
M/IO#
D/C#
W/R#
ADS#
AHOLD
CACHE#
BE7#–BE0#
SCYC
HLDA
RESET
D/P#
CLK
Latched
ADS#
Delayed
Latched
Address
Delayed
Data
LAST_D
DVALID_D
Master sample
[
D63-D0
All other control
signals
Master sample
[
D63-D0
All other
control signals
Sample point 1
A31-A0
M/IO#
D/C#
W/R#
ADS#
AHOLD
CACHE#
BE7#–BE0#
SCYC
HLDA
RESET
D/P#
Master sample
[
D63-D0
All other
control signals
Master sample
[
D63-D0
All other
control signals
Master sample
[
D63-D0
All other
control signals
[
Channels not set up in a channel group by the TMS 109A Socket 7 software are logged with the Master sample.
Figure 2–1: Nonpipelined single and Burst Transfer cycles
Relative to real time, nondelayed Socket 7 microprocessor signals, the first
sample point in a cycle occurs two clocks after the ADS# signal is asserted. The
second (and subsequent, if the cycle is a burst) sample point occurs two clocks
after the BRDY# or BRDYC# signal.
Figure 2–2 shows a single cycle transfer pipelined into another single cycle
transfer. The ADS#, Address and Data signal forms are delayed by two CLK
cycles. This diagram also shows the timing relationships of D_LAST,