Tektronix Socket 7 TMS109A, Instruction Manual

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Acquiring and Viewing Disassembled Data
TMS 109A Socket 7 Microprocessor Support
2–23
Figure 2–9: Hardware display for the AMD Bus cycles
Speculative prefetch cycles can occur when the Socket 7 microprocessor fetches
instructions that have been previously executed. To minimize prefetch delays, the
Socket 7 microprocessor predicts the outcome of the branch instruction and starts
prefetching at that address. When the branch instruction is executed, the target
address is determined. If the Socket 7 microprocessor predicted the target address
correctly, then the needed code has already been fetched. If it did not correctly
predict the target address, then the speculative prefetch cycles that had been
fetched will be flushed and fetching will begin at the target address.
Figure 2–10 shows an example of speculative prefetch cycles. The previous time
(not shown) that the JNE instruction was executed, the branch was taken and the
new target address was 0x3893D. The microprocessor assumed that the address
would be 0x3893D and so started fetching at 0x38938 (which contains
0x3893D). Cycles at samples 746 and 748 are speculative prefetch cycles. When
the instruction was executed, the microprocessor determined that the branch was
Speculative Prefetch
Cycles