Tektronix Socket 7 TMS109A, Instruction Manual

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TMS 109A Socket 7 Microprocessor Support
Index–1
Index
Numbers
3DNow! instruction set, 2–25
40 MHz system under test, 1–4
A
about this manual set, ix
acquiring data, 2–9
below 40 MHz, 1–4
Acquisition Setup, 1–20
Address, channel assignments, 1–14
Address group, display column, 2–14
Address Synthesis Jumpers, Address Synthesis, 1–6
AHOLD signal, during Writeback cycle, 1–2
Alternate Bus Master cycles, 2–4
Alternate Connections, ITP, 1–10
asterisks, indicates out-of-order fetch, 2–21
B
branch trace messages, 2–21
Burst cycles, addresses in state data, 1–2
burst cycles, 2–24
bus anomalies, 1–3
bus cycles, displayed cycle types, 2–12
Bus Hold cycles, 1–2
C
Cache, channel assignments, 1–19
cache, instruction, 1–2
Cache Invalidation cycles, 1–2, 2–24
channel assignments
Address, 1–14
Cache, 1–19
clocks and QUAL, 1–20
control, 1–18
Data, 1–15
Data Size, 1–19
Data_Lo, 1–17
Misc, 1–19
Signals not connected, 1–21, 1–22
signals not required, 1–21
Signals on the Probe Adapter, 1–21
channel groups, 2–1
Chip Set mode, 2–5
clock and QUAL channel assignments, 1–20
clock channel assignments, 1–21
clock rate, 1–2
clocking, Custom, how data is acquired, 2–1
Code Segment Size field, 2–18
connections
CPU to Mictor, 1–22
microprocessor removal, 1–7
probe adapter to SUT, 1–6
sockets, 1–8
Control, channel assignments, 1–18
Control Flow display format, 2–15
Control group, symbol table, 2–5
CPU to Mictor connections, 1–22
Custom clocking, how data is acquired, 2–1
cycle types, 2–12
D
D/P# Signal Jumper, 1–5
Data, channel assignments, 1–15
data
acquiring, 2–9
disassembly formats
data display, changing, 2–17
Data group, display column, 2–14
Data Size, channel assignments, 1–19
Data_Lo, channel assignments, 1–17
Data_Lo group, display column, 2–14
definitions
disassembler, ix
information on basic operations, ix
demonstration file, 2–28
Descriptor Table reads and writes, 1–3
dimensions, probe adapter, 3–4
Directory Table reads and writes, 1–3
disassembled data
cycle type definitions, 2–12
viewing, 2–9
viewing an example, 2–28
disassembler
definition, ix
logic analyzer configuration, 1–1
setup, 2–1
Disassembly Format Definition overlay, 2–17
Disassembly property page, 2–17