Tektronix Socket 7 TMS109A, Instruction Manual

Page: 49 / 113

Setting Up the Support
TMS 109A Socket 7 Microprocessor Support
2–3
DVALID_D, and PIPE_D, which are the signals synthesized by sequential logic
in the PALs.
CLK
Latched
ADS#
Delayed
Address
Delayed
Data
LAST_D
DVALID_D
PIPE_D
Sample point 1
A31-A0
M/IO#
D/C#
W/R#
ADS#
AHOLD
CACHE#
BE7#–BE0#
SCYC
HLDA
RESET
Master sample
[
D63-D0
All other
control signals
Sample point 1
A31-A0
M/IO#
D/C#
W/R#
ADS#
AHOLD
CACHE#
BE7#–BE0#
SCYC
HLDA
RESET
Master sample
[
D63-D0
All other
control signals
[
Channels not set up in a channel group by the TMS 109A Socket 7 software are logged with the Master sample.
Figure 2–2: Pipelined cycles
With relationship to real-time, nondelayed, Socket 7 microprocessor signals, the
first sample point in a cycle occurs two clocks after the ADS# signal is asserted.
When the ADS# signal is asserted again to pipeline a second cycle into the first,
the first sample point for that second cycle occurs three clocks after the last
BRDY# or BRDYC# signal is returned from the first outstanding cycle.
The clocking algorithm for the Socket 7 microprocessor has two variations:
Alternate Bus Master Cycles Excluded and Alternate Bus Master Cycles
Included.
ClockingOptions