Tektronix Socket 7 TMS109A, Instruction Manual

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Setting Up the Support
TMS 109A Socket 7 Microprocessor Support
2–5
Mode Differences
The Socket 7 microprocessor can operate in either Component or Chip Set mode.
In Component mode (stand alone), the microprocessor interfaces directly to the
system bus.
The Socket 7 microprocessor, C5C cache controller, and the C8C cache memory
(SRAM) can be combined to form a chip set or enhanced design. The two cache
devices connect to the system bus and a memory bus controller interfaces to the
microprocessor and cache devices.
The behavior of the Socket 7 microprocessor is affected when operating in Chip
Set mode. The TMS 109A Socket 7 software and probe adapter still supports the
Socket 7 microprocessor in this mode.
There are also two new signals: BRDYC# (pin L3) and ADSC# (pin N4).
In Component mode, the BRDYC# signal is seen as a “no connect” pin. The
TMS 109A Socket 7 probe adapter uses the BRDYC# signal for clocking when it
is active. The probe adapter has a pullup resistor on this line to hold it inactive
when the Socket 7 is in Chip-Set mode. The BRDYC# signal can be probed on
C1:0.
In Component mode, the ADSC# signal is seen as a “no connect” pin and is not
used for clocking by the probe adapter.
Symbols
The TMS 109A Socket 7 support supplies one symbol table file. The SOCK-
ET7_Ctrl file replaces specific Control channel group values with symbolic
values when Symbolic is the radix for the channel group.
Table 2–1 shows the name, bit pattern, and meaning for the symbols in the file
SOCKET7_Ctrl, the Control channel group symbol table.
Table 2–1: Control group symbol table definitions
Control group value
Symbol
PRDY SCYC BOFF3#
D/P# BUSCHK# LAST_D M/IO#
INIT SMIACT# AHOLD D/C#
IRESET_L LOCK# HLDA W/R#
Meaning
Reset
Primary processor opcode read
Dual processor opcode read
Component Mode
Chip Set Mode