Tektronix Socket 7 TMS109A, Instruction Manual

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Acquiring and Viewing Disassembled Data
TMS 109A Socket 7 Microprocessor Support
2–25
separate, alternate memory space called SMRAM. The disassembler uses
information from the SMIACT# signal to determine when the Socket 7 micropro-
cessor is operating in this mode.
The Socket 7 microprocessor includes the MMX instruction set. Since these
instructions are potential subroutine instructions, the disassembler checks to see
if an interrupt level 6 (illegal opcode) or 7 (device not available) occurred. If an
interrupt 6 or 7 occurs, the interrupt will flush the bus.
When the disassembler detects that an instruction is from the MMX set, it
displays an (MMX) to the right of the mnemonic.
MMX instructions are disassembled whether or not the microprocessor is set up
to execute them.
The Socket 7 microprocessor includes the 3DNow! instruction set which support
s
AMD-K6-2
. When the disassembly detects that an instruction is from the 3DNow!
set, it displays (3DNow!) to the right of the mnemonics.
The disassembler has a Mark Opcode function that allows you to change the
interpretation of a cycle type. Using this function, you can select a cycle and
change it to one of the following cycle types:
H
Opcode & Flush Previous (marks the first word of an instruction and the
lower bytes of this cycle as flushed)
H
Opcode ( marks the first word of an instruction)
H
Flush to end (flushes the current byte to the high end of the sample)
H
Flush (marks an opcode or extension that is fetched but not executed)
H
Undo (clears all marks on this byte)
H
Flush Cycle (the entire cycle was fetched, but not executed (opcode or
extension))
H
16-bit or 32-bit default segment size
Mark selections are as follows:
Lo: -- -- -- 00
Lo: -- -- 11 --
Lo: -- 22 -- --
Lo: 33 -- -- --
Hi: -- -- -- 44
Hi: -- -- 55 --
Hi: -- 66 -- --
MMX Instruction Set
3DNow!
Marking Cycles