Tektronix Socket 7 TMS109A, Instruction Manual

Page: 18 / 113

Getting Started
1–2
TMS 109A Socket 7 Microprocessor Support
Refer to information on basic operations to determine how many modules and
probes your logic analyzer needs to meet the minimum channel requirements for
the TMS 109A Socket 7 microprocessor support.
Requirements and Restrictions
You should review the general requirements and restrictions of microprocessor
supports in the information on basic operations as they pertain to your system
under test.
You should also review electrical, environmental, and mechanical specifications
in the Specifications chapter in this manual as they pertain to your system under
test, as well as the following descriptions of other Socket 7 support requirements
and restrictions.
System Clock Rate.
The TMS 109A Socket 7 support can acquire data from the
Socket 7 microprocessors at bus speeds of up to 100 MHz; the tested clock speed
is 100 MHz. This specification is valid at the time this manual was printed.
Contact your Tektronix sales representative for current information on the fastest
devices supported.
System Under Test Power.
Whenever the system under test is powered off, be sure
to remove power from the probe adapter. Refer to Applying and Removing Power
on page 1–13 for information on how to remove power from the probe adapter.
Disabling the Instruction Cache.
To disassemble acquired data, you must disable
the internal instruction cache. Disabling the cache makes all instruction
prefetches visible on the bus so they can be acquired and disassembled.
Cache Invalidation Cycles. Cache Invalidation addresses are not acquired.
Bus Hold Cycles.
Bus Hold cycles are not acquired while the RESET signal is
active.
AHOLD Signal.
If the AHOLD signal is active (high) during a Writeback cycle (a
four cycle Burst Write), the acquired address is undefined.
Burst Cycles. The Socket 7 microprocessor expects the memory system to
increment addresses during a Burst cycle. When viewing disassembled data, the
disassembler synthesizes the addresses. When viewing state data, the addresses
appear to be identical.