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Tektronix Socket 7 TMS109A, Instruction Manual

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Tektronix Socket 7 TMS109A Instruction Manual Download Page 52

Setting Up the Support

2–6

TMS 109A Socket 7 Microprocessor Support

Table 2–1: Control group symbol table definitions (cont.)

Control group value

Symbol

Meaning

PRDY

SCYC

BOFF3#

D/P#

BUSCHK#

LAST_D

M/IO#

INIT

SMIACT#

AHOLD

D/C#

IRESET_L

LOCK#

HLDA

W/R#

FETCH*

X X 0

X X X 1

X X X 0

1 1 0 0

Opcode read

P_LOCK_RD

0 X 0

X X X 0

X X X 0

1 X 1 0

Primary processor locked read cycle

D_LOCK_RD

1 X 0

X X X 0

X X X 0

1 X 1 0

Dual processor locked read cycle

LOCK_RD*

X X 0

X X X 0

X X X 0

1 X 1 0

Locked read cycle

P_LOCK_WR

0 X 0

X X X 0

X X X 0

1 X 1 1

Primary processor locked write cycle

D_LOCK_WR

1 X 0

X X X 0

X X X 0

1 X 1 1

Dual processor locked write cycle

LOCK_WR*

X X 0

X X X 0

X X X 0

1 X 1 1

Locked write cycle

P_MEM_RD

0 X 0

X X X X

X X X 0

1 1 1 0

Primary processor nonopcode read

D_MEM_RD

1 X 0

X X X X

X X X 0

1 1 1 0

Dual processor nonopcode read

MEM_RD*

X X 0

X X X X

X X X 0

1 1 1 0

Read from memory, nonopcode

P_MEM_WR

0 X 0

X X X X

X X X 0

1 1 1 1

Primary processor write to memory

D_MEM_WR

1 X 0

X X X X

X X X 0

1 1 1 1

Dual processor write to memory

MEM_WR*

X X 0

X X X X

X X X 0

1 1 1 1

Write to memory

P_I/O_RD

0 X 0

X X X X

X X X 0

1 0 1 0

Primary processor I/O read cycle

D_I/O_RD

1 X 0

X X X X

X X X 0

1 0 1 0

Dual processor I/O read cycle

I/O_RD*

X X 0

X X X X

X X X 0

1 0 1 0

I/O read cycle

P_I/O_WR

0 X 0

X X X X

X X X 0

1 0 1 1

Primary processor I/O write cycle

D_I/O_WR

1 X 0

X X X X

X X X 0

1 0 1 1

Dual processor I/O write cycle

I/O_WR*

X X 0

X X X X

X X X 0

1 0 1 1

I/O write cycle

P_MEM_R/W*

0 X 0

X X X X

X X X 0

1 1 1 X

Any primary processor read or write

D_MEM_R/W*

1 X 0

X X X X

X X X 0

1 1 1 X

Any dual processor read or write

MEM_R/W*

X X 0

X X X X

X X X 0

1 1 1 X

Any memory read or write cycle

P_I/O_R/W*

0 X 0

X X X X

X X X 0

1 0 1 X

Any primary processor I/O cycle

D_I/O_R/W*

1 X 0

X X X X

X X X 0

1 0 1 X

Any dual processor I/O cycle

I/O_R/W*

X X 0

X X X X

X X X 0

1 0 1 X

Any I/O read or write cycle

P_READ*

0 X 0

X X X X

X X X 0

1 X 1 0

Any primary processor read cycle

D_READ*

1 X 0

X X X X

X X X 0

1 X 1 0

Any dual processor read cycle

READ*

X X 0

X X X X

X X X 0

1 X 1 0

Any read cycle

P_WRITE*

0 X 0

X X X X

X X X 0

1 X 1 1

Any primary processor write cycle

D_WRITE*

1 X 0

X X X X

X X X 0

1 X 1 1

Any dual processor write cycle

WRITE*

X X 0

X X X X

X X X 0

1 X 1 1

Any write cycle

P_INT_ACK

0 X 0

X X X X

X X X 0

1 0 0 0

Primary processor int. acknowledge

Summary of Contents for Socket 7 TMS109A

Page 1: ...essor Support 071 0497 01 Warning The servicing instructions are for use by qualified personnel only To avoid personal injury do not perform any servicing unless you are qualified to do so Refer to al...

Page 2: ...hnical Data and Computer Software clause at DFARS 252 227 7013 or subparagraphs c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Tektronix products...

Page 3: ...ce under this warranty Customer must notify Tektronix of the defect before the expiration of the warranty period If Tektronix is unable to provide a replacement that is free from defects in materials...

Page 4: ...locations This warranty shall not apply to any defect failure or damage caused by improper use or improper or inadequate maintenance and care Tektronix shall not be obligated to furnish service under...

Page 5: ...is Jumper 1 6 Connecting to a System Under Test 1 6 Connect the P6434 Probes to the Probe Adapter 1 6 Remove the Microprocessor 1 7 Choose a Protective Socket 1 8 Insert Probe Adapter 1 9 Insert Micro...

Page 6: ...21 Out Of Order Fetches 2 21 Speculative Prefetch Cycles 2 23 Cache Invalidation Cycles 2 24 Burst Cycles 2 24 System Management Mode SMM 2 24 MMX Instruction Set 2 25 3DNow 2 25 Marking Cycles 2 25...

Page 7: ...1 22 Figure 2 1 Nonpipelined single and Burst Transfer cycles 2 2 Figure 2 2 Pipelined cycles 2 3 Figure 2 3 Hardware display format 2 14 Figure 2 4 Data displayed from the Primary and Dual microproc...

Page 8: ...bly 1 21 Table 1 13 Signals on the probe adapter but not acquired 1 21 Table 1 14 Signals not connected to probe adapter 1 21 Table 1 15 CPU to Mictor connections for Mictor A pins 1 23 Table 1 16 CPU...

Page 9: ...ement instrument Ground the Product This product is indirectly grounded through the grounding conductor of the mainframe power cord To avoid electric shock the grounding conductor must be connected to...

Page 10: ...lt in injury or loss of life CAUTION Caution statements identify conditions or practices that could result in damage to this product or other property Terms on the Product These terms may appear on th...

Page 11: ...product unless another person capable of rendering first aid and resuscitation is present Disconnect Power To avoid electric shock switch off the instrument power then disconnect the power cord from...

Page 12: ...Service Safety Summary viii TMS 109A Socket 7 Microprocessor Support...

Page 13: ...plement this instruction manual with information on basic operations to set up and run the support NOTE The disassembly software is optimized to decode instruction streams and bus activities from Inte...

Page 14: ...pport outside of North America contact your local Tektronix distributor or sales office Service Support Tektronix offers extended warranty and calibration programs as options on many products Contact...

Page 15: ...Getting Started...

Page 16: ......

Page 17: ...a 136 chan nel module A complete list of standard and optional accessories is provided at the end of the parts list in the Replaceable Parts List chapter To use this support efficiently you must have...

Page 18: ...time this manual was printed Contact your Tektronix sales representative for current information on the fastest devices supported System Under Test Power Whenever the system under test is powered off...

Page 19: ...ways loads 32 bytes starting from the most significant octabyte octet in the block For example these addresses 00 08 10 and18 would be fetched in this order 18 10 08 and 00 Regardless of what the crit...

Page 20: ...f the socket being probed Acquires the D P signal from an external source If this jumper is left open you must route the D P signal to pin 1 of this jumper from an external source This allows you to p...

Page 21: ...racking J240 MFG_TEST J250 CLK Figure 1 1 Jumper locations on the probe adapter Place the Processor Selection jumper J900 in the 1 2 position to support microprocessors that do not have the D P pin Pl...

Page 22: ...per J921 on the probe adapter is in position 1 2 A 2 0 is derived from the BE 7 0 signals and stored in the acquisition memory with the rest of the address When the jumper is in position 2 3 it disabl...

Page 23: ...to the probe and probe adapter always position the probe perpendicular to the mating connector and gently connect the probe Incorrect handling of the P6434 probe while connecting it to the probe adapt...

Page 24: ...from the system under test and from the bottom of the probe adapter assembly For the 321 pin processor Fro the 296 pin processor Black holes are no pins Figure 1 3 Protective sockets 8 Align the A3 p...

Page 25: ...r Support 1 9 11 Insert the probe adapter into the installed protective socket as shown in Figure 1 4 System under test Pin A3 Pin A3 socket Protective Figure 1 4 Placing the socket and probe adapter...

Page 26: ...p the components on the probe adapter cool Alternate Connections NOTE Refer to the Intel document ITP700 Port Users Guide for more informa tion on the ITP interface The Socket 7 probe adapter provides...

Page 27: ...he pin to signal assignments of the In Target Probe ITP connector J580 on the probe adapter Table 1 2 ITP J580 signal Information Pin number Signal name 1 B_INIT 2 DBRESET 3 B_RESET 4 GND 5 6 3 3 V 7...

Page 28: ...ure 1 6 shows the location Table 1 3 J260 jumper pin assignments Jumper pin number Socket 7 signal name 1 OC_DBRESET Open Collector active low version of DBRESET 2 NC 3 DBRESET The probe adapter conta...

Page 29: ...robe adapter To apply power to the Socket 7 probe adapter and system under test follow these steps CAUTION To prevent possible permanent damage to the probe adapter and Socket 7 microprocessor use the...

Page 30: ...icates that it is double probed H Channels are shown starting with the most significant bit MSB descending to the least significant bit LSB The channel group assignment tables for disassembly and Timi...

Page 31: ...0 A2 4 A20 19 A2 3 A19 18 A2 2 A18 17 A2 1 A17 16 A2 0 A16 15 A1 7 A15 14 A1 6 A14 13 A1 5 A13 12 A1 4 A12 11 A1 3 A11 10 A1 2 A10 9 A1 1 A9 8 A1 0 A8 7 A0 7 A7 6 A0 6 A6 5 A0 5 A5 4 A0 4 A4 3 A0 3 A3...

Page 32: ...30 E3 6 D62 29 E3 5 D61 28 E3 4 D60 27 E3 3 D59 26 E3 2 D58 25 E3 1 D57 24 E3 0 D56 23 E2 7 D55 22 E2 6 D54 21 E2 5 D53 20 E2 4 D52 19 E2 3 D51 18 E2 2 D50 17 E2 1 D49 16 E2 0 D48 15 E1 7 D47 14 E1 6...

Page 33: ...displayed in hexadecimal Table 1 6 Data_Lo channel group assignments Bit order Section channel Socket 7 signal name 31 D3 7 D31 30 D3 6 D30 29 D3 5 D29 28 D3 4 D28 27 D3 3 D27 26 D3 2 D26 25 D3 1 D25...

Page 34: ...rocessor signal for each channel connect The symbol table file name is SOCKET7_Ctrl By default the Control channel group assignments are displayed as symbols Table 1 7 Control channel group assignment...

Page 35: ...is asserted LOW Table 1 9 lists the probe section and channel assignments for the Cache group and the microprocessor signal for each channel connect By default the Cache channel group assignments are...

Page 36: ...ID_D CLK 1 PIPE_D CLK 2 LAST_D CLK 3 CLK C2 0 RESET_L C2 1 BOFF C2 2 HLDA C2 3 ADS QUAL 0 Not Used QUAL 1 Not Used QUAL 2 Not Used QUAL 3 Not Used Indicates the channel is asserted low Acquisition Set...

Page 37: ...channel is asserted low Table 1 13 lists signals on the probe adapter but not acquired Table 1 13 Signals on the probe adapter but not acquired Signal name AUX J580 Pin number TDI 12 TDO 13 TMS 14 TCK...

Page 38: ...x for more information on mechanical specifications Tables 1 15 through 1 17 show the CPU pin to Mictor pin connections Tektronix uses a counterclockwise pin assignment Pin 1 is located at the top lef...

Page 39: ...7 AG 33 9 17 A3 2 A26 AH 34 10 19 A3 1 A25 AJ 35 11 21 A3 0 A24 AG 35 12 23 A2 7 A23 AE 33 13 25 A2 6 A22 AH 36 14 27 A2 5 A21 AF 34 15 29 A2 4 A20 AL 21 16 31 A2 3 A19 AK 22 17 33 A2 2 A18 AL 23 18 3...

Page 40: ...GND GND GND 44 44 GND GND GND Table 1 16 CPU to Mictor connections for Mictor D pins Tektronix Mictor D pin number AMP Mictor D pin number LA channel Socket 7 signal name Socket 7 pin number 1 1 GND...

Page 41: ...D1 0 D8 D 34 29 20 D1 1 D9 C 37 30 18 D1 2 D10 C 35 31 16 D1 3 D11 B 36 32 14 D1 4 D12 D 32 33 12 D1 5 D13 B 34 34 10 D1 6 D14 C 33 35 8 D1 7 D15 A 35 36 6 CLOCK 2 LAST_D DERIVED 37 4 GND GND GND 38 2...

Page 42: ...D55 G 03 13 25 E2 6 D54 E 01 14 27 E2 5 D53 G 05 15 29 E2 4 D52 E 03 16 31 E2 3 D51 F 04 17 33 E2 2 D50 D 02 18 35 E2 1 D49 E 05 19 37 E2 0 D48 D 04 20 38 E0 0 D32 C 15 21 36 E0 1 D33 D 16 22 34 E0 2...

Page 43: ...cket 7 signal name Socket 7 pin number 1 1 GND GND GND 2 3 GND GND GND 3 5 CLOCK 3 CLK AK 18 4 7 C3 7 D C AK 04 5 9 C3 6 PRDY AC 05 6 11 C3 5 BUSCHK AL 07 7 13 C3 4 BRDY DERIVED 8 15 C3 3 W R DERIVED...

Page 44: ...Mictor C pin number 27 24 C0 7 D P DERIVED 28 22 C1 0 BE0 AL 09 29 20 C1 1 BE1 AK 10 30 18 C1 2 BE2 AL 11 31 16 C1 3 BE3 AK 12 32 14 C1 4 BE4 AL 13 33 12 C1 5 BE5 AK 14 34 10 C1 6 BE6 AL 15 35 8 C1 7...

Page 45: ...Operating Basics...

Page 46: ......

Page 47: ...ovides default values for each of these setups but you can change them as needed Channel Group Definitions The software automatically defines channel groups for the support The channel groups for the...

Page 48: ...W R ADS AHOLD CACHE BE7 BE0 SCYC HLDA RESET D P Master sample D63 D0 All other control signals Master sample D63 D0 All other control signals Master sample D63 D0 All other control signals Channels n...

Page 49: ...t set up in a channel group by the TMS 109A Socket 7 software are logged with the Master sample Figure 2 2 Pipelined cycles With relationship to real time nondelayed Socket 7 microprocessor signals th...

Page 50: ...nals the bus activity is logged in like normal bus cycles except that the HLDA signal is high H If none of the control lines are driven or if the Socket 7 microprocessor can not see them the module wi...

Page 51: ...YC signal is seen as a no connect pin The TMS 109A Socket 7 probe adapter uses the BRDYC signal for clocking when it is active The probe adapter has a pullup resistor on this line to hold it inactive...

Page 52: ...1 Write to memory P_I O_RD 0 X 0 X X X X X X X 0 1 0 1 0 Primary processor I O read cycle D_I O_RD 1 X 0 X X X X X X X 0 1 0 1 0 Dual processor I O read cycle I O_RD X X 0 X X X X X X X 0 1 0 1 0 I O...

Page 53: ...X X X 0 1 X X X Primary processor buscheck D_BUSCHCK 1 X 0 X 0 X X X X X 0 1 X X X Dual processor buscheck BUSCHCK 0 X 0 X 0 X X X X X 0 1 X X X Buscheck P_LOCKED 0 X 0 X 1 X 0 X X X X X X X X Any pr...

Page 54: ...Setting Up the Support 2 8 TMS 109A Socket 7 Microprocessor Support...

Page 55: ...level source debug capabilities of a Tektronix logic analyzer Consult your Tektronix field office for future enhancements Acquiring Data Once you load the SOCKET7_ support choose a clocking mode and...

Page 56: ...in decimal Example 12t for 0xC in hexadecimal Indicates there is insufficient data available for complete disassembly of the instruction the number of asterisks indicates the width of the data that i...

Page 57: ...e the display of disassembled data from both data groups the disassembler may display more than one line for each data sample For samples with two display lines data displayed under the Data column of...

Page 58: ...instruction and a READ EXTENSION or FLUSH or both Table 2 3 Cycle type definitions Label Description RESET A reset cycle MEM READ A nonlocked memory read cycle that is not an opcode fetch LOCKED MEM...

Page 59: ...T LINE FILL Fetch cycle computed to be a burst fill The data is fetched but will not be executed it is part of a 32 byte fetch It will possibly be stored in cache BACKOFF BURST FLUSH Burst Fetch cycle...

Page 60: ...SI 0000000E 32 25 000408C0 44875050 DUAL FETCH 100 ns 000408C4 04870824 DUAL FETCH 5 6 7 Figure 2 3 Hardware display format 1 Sample Column Lists the memory locations for the acquired data 2 Address G...

Page 61: ...e instructions you will have to switch to the Hardware display format You also cannot mark an out of order fetch in software mode you must switch to hardware mode The Control Flow display format shows...

Page 62: ...WD PUNPCKLBW PUNPCKLDQ PUNPCKLWD PXOR The Subroutine display format shows only the first fetch of subroutine call and return instructions It will display conditional subroutine calls if they are consi...

Page 63: ...unique to the Socket 7 support to do the following tasks H Change how data is displayed across all display formats H Change the interpretation of disassembled cycles H Display exception vectors NOTE A...

Page 64: ...r AMD depending on the socket7 processor that is under test The TMS 109A Socket 7 support has been tested with both these microprocessor venders Other Processor The other microprocessor is the one not...

Page 65: ...icates data from the other microprocessor Sample Address Data Mnemonic Control 16 000388B0 ABFFE1C3 RETS 32 P_FETCH 000388B4 B6EFFFEF FLUSH P_FETCH 17 000408A8 ED33D233 DUAL FETCH D_FETCH 000408AC FF3...

Page 66: ...026A PUSH 02 32 P_FETCH 0003881A 4668026A PUSH 00000046 32 P_FETCH 0003881F 6A000000 PUSH 02 32 P_FETCH Figure 2 5 Disassembled data displayed from the Primary microprocessor only Figure 2 6 shows dis...

Page 67: ...t and source Branch Trace Messages The Socket 7 microprocessor can prefetch cycles out of ascending order For example a branch to address 1008 could cause the following sample of addresses across the...

Page 68: ...In the Software display format out of order fetches are displayed in the order they were executed see Figure 2 8 If the previously executed instruction had a larger sample number than the out of order...

Page 69: ...target address correctly then the needed code has already been fetched If it did not correctly predict the target address then the speculative prefetch cycles that had been fetched will be flushed an...

Page 70: ...ften performs speculative prefetching of branch target addresses no matter if they are taken or are not taken The disassembler usually interprets the correct flow of execution but cannot do so determi...

Page 71: ...Socket 7 microprocessor includes the 3DNow instruction set which supports AMD K6 2 When the disassembly detects that an instruction is from the 3DNow set it displays 3DNow to the right of the mnemoni...

Page 72: ...ence number you must switch to hardware mode to mark that sequence See Out Of Order Fetches on page 2 21 and Software Display Format on page 2 15 Information on basic operations contains more details...

Page 73: ...6 0018 7 001C 8 0020 9 0024 10 0028 11 002C 12 0030 13 0034 14 15 0038 003C 16 0040 17 31 0044 007C 32 255 0080 03FC IV means interrupt vector Table 2 6 lists the Socket 7 exception vectors for the P...

Page 74: ...8 IDT means interrupt descriptor table Viewing an Example of Disassembled Data A demonstration system file or demonstration reference memory is provided so you can see an example of how your Socket 7...

Page 75: ...Specifications...

Page 76: ......

Page 77: ...gure showing the logic analyzer connected to a typical probe adapter Refer to that figure while reading the following description The probe adapter consists of a circuit board and two sockets for a So...

Page 78: ...haracteristics Requirements System under test DC power requirements Voltage 4 75 5 25 VDC Current I maximum calculated 1 8 A I typical measured 1 2 A Probe adapter power supply requirements Voltage 90...

Page 79: ...Minimum operating 0 C 32 F Non operating 55 C to 75 C 67 to 167 F Humidity 10 to 95 relative humidity Altitude Operating 4 5 km 15 000 ft maximum Non operating 15 km 50 000 ft maximum Electrostatic i...

Page 80: ...A Socket 7 Microprocessor Support Figure 3 1 shows the dimensions of the probe adapter 6 60 mm 260 in 118 87 mm 4 680 in 40 64 mm 1 600 in 121 41 mm 4 780 in 51 05 mm 2 010 in Pin A3 Figure 3 1 Dimens...

Page 81: ...re for use only by qualified personnel To avoid injury do not perform any servicing other than that stated in the operating instructions unless you are qualified to do so Refer to all Safety Summaries...

Page 82: ......

Page 83: ...Maintenance...

Page 84: ......

Page 85: ...on from the Socket 7 microprocessor bus The CSM is tightly linked to the processor bus T states and is synchronized to the Socket 7 microprocessor on a clock by clock basis It is possible that unpredi...

Page 86: ...cket 7 signal delays when using the probe adapter Table 4 1 Socket 7 signal delays using the probe adapter Signal name Hardware CLK delays Firmware CLK delays A31 3 D63 0 BE7 0 D C M IO PRDY LOCK BUSC...

Page 87: ...Diagrams...

Page 88: ......

Page 89: ...number for example A5 The assembly number appears in the title on the diagram in the lookup table for the schematic diagram and corresponding component locator illustration The Replaceable Electrical...

Page 90: ...5 2 TMS 109A Socket 7 Hardware Support...

Page 91: ...5 3 TMS 109A Socket 7 Microprocessor Support...

Page 92: ...TMS 109A Socket 7 Microprocessor Support 5 4 A1 Socket 7 Circuit Board Front A23 A2 R1234 COMPONENT NUMBER EXAMPLE A1 Socket 7 Circuit Board Back...

Page 93: ...25 26 12 8 19 13 11 15 16 18 14 10 9 17 4 5 2 3 1 0 59 58 51 23 26 21 20 22 24 43 41 25 27 29 31 28 30 33 32 42 46 40 44 47 45 39 49 38 37 36 35 34 48 50 52 53 54 55 56 57 60 62 61 63 15 14 13 12 11...

Page 94: ...TMS 109A Socket 7 Microprocessor Support 5 6...

Page 95: ...8 9 10 11 3 2 6 5 4 7 8 11 10 9 3 4 5 6 8 7 9 10 11 6 5 4 3 11 10 9 7 8 46 45 44 48 47 50 51 49 53 52 54 56 55 58 57 60 61 62 13 14 12 15 16 18 19 17 20 21 14 13 12 16 15 18 19 17 21 20 22 23 24 25 2...

Page 96: ...TMS 109A Socket 7 Microprocessor Support 5 8...

Page 97: ...THIS JUMPER EXTERNALLY IF PROBING FROM THE DUAL SOCKET D P FROM THE PRIMARY SOCKET TO BTRACK RST RW_ADS LATCH SYNTH R_S B_RESET B_INIT L_A1 L_A2 L_A0 2 1 0 D_LAST D_PIPE D_DVALID L_HLDA L_BRDY L_ADS L...

Page 98: ...TMS 109A Socket 7 Microprocessor Support 5 10...

Page 99: ...8 R_A 7 R_A 6 R_A 5 R_A 4 R_A 3 R_A 16 R_A 17 R_A 18 R_A 19 R_A 20 R_A 21 R_A 22 R_A 23 R_A 24 R_A 25 R_A 26 R_A 27 R_A 28 R_A 29 R_A 30 R_A 31 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 32 33 3...

Page 100: ...TMS 109A Socket 7 Microprocessor Support 5 12...

Page 101: ...Replaceable Parts...

Page 102: ......

Page 103: ...erefore when ordering parts it is important to include the following information in your order H Part number H Instrument type or model number H Instrument serial number H Instrument modification numb...

Page 104: ...NC 825 OLD TRAIL ROAD ETTERS PA 17319 9769 26742 METHODE ELECTRONICS INC BACKPLAIN DIVISION 7444 WEST WILSON AVE CHICAGO IL 60656 4548 60381 PRECISION INTERCONNECT CORP 16640 SW 72ND AVE PORTLAND OR 9...

Page 105: ...N CTR 0 10 X 0 10 CTR 0 165 H X 0 125 TAIL 30 63058 PZA 63150 001 8 131 6610 00 1 JACK POWER DC PCB MALE RTANG 2MM D PIN BRASS SILVER PLATE 5A 82389 RAPC722TB 9 159 0059 00 1 FUSE WIRE LEAD 5A 125V 61...

Page 106: ...rial no effective Tektronix part number 161 0104 07 1 CA ASSY PWR 3 1 0MM SQ 240V 10A 2 5 METER RTANG IEC320 RCPT X 13A FUSED UK PLUG 13A FUSE TK2541 ORDER BY DESCRIPTION 161 0167 00 1 CA ASSY PWR 3 0...

Page 107: ...Replaceable Parts TMS 109A Socket 7 Microprocessor Support 6 5 1 2 3 4 5 6 7 8 9 10 11 12 Figure 6 1 TMS 109A Socket 7 probe adapter exploded view...

Page 108: ...Replaceable Parts 6 6 TMS 109A Socket 7 Microprocessor Support...

Page 109: ...Index...

Page 110: ......

Page 111: ...annel groups 2 1 Chip Set mode 2 5 clock and QUAL channel assignments 1 20 clock channel assignments 1 21 clock rate 1 2 clocking Custom how data is acquired 2 1 Code Segment Size field 2 18 connectio...

Page 112: ...1 5 D P Signal 1 5 MFG_TEST 1 4 Processor Selection 1 5 Tracking 1 6 L logic analyzer configuration for disassembler 1 1 software compatibility 1 1 M manual conventions ix how to use the set ix Mark C...

Page 113: ...10 indicates an immediate value 2 10 indicates bus cycle from Other processor 2 10 asterisk to indicate out of order fetches 2 21 indicates insufficient data avaliable 2 10 more 2 22 indicates insuff...

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