STC SmartScanIS, User Manual

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14 January 2021, SmartScanIS User’s Guide for Union Pacific, EUD-2016026-00 Rev.2
The Processor board uses two, independently operating, central processing units ( CPUs ).
The CPU on the left (aka processor-A aka Analyzer Processor) is responsible for data retrieval
from most external sources, such as the shielded temperature probe, scanners, transducers,
and dragging-equipment detectors. The CPU on the right (aka processor-B aka
Communications Processor) is used to process and store the data retrieved by the other CPU.
Also, the CPU on the right is responsible for data retrieval from the remaining external
sources, such as the wind monitor. After the train data is stored, the system can send it to the
user in the form of a report or through the polling system.
Processor-A initially stores train data in static random-access memory (SRAM) on the
Processor board. After train passage, processor-B moves this data to a different SRAM for
longterm storage. This SRAM contains:

The Trains directory, which contains data on each new train that passes the site and
each new generated gate-test train. The Train Summary report and Train Detail report
get their data from this directory. The Last Train report, Range of Trains report, and
T94 Train Detail report also get their data from this directory.

The Exceptions directory, which contains data on each train that has one or more
Exception Alarms or on a train where sliding wheels were detected. The Exception
Summary report and Exception Detail report get their data from this directory.
Each directory is organized as a circular buffer. In this scheme, data is added to the directory
until the directory is full. Once full, the oldest data in the directory is overwritten as new data is
recorded. The buffer for the Trains directory holds data on about 88,000 axles, but no more
than 300 trains. The buffer for the Exceptions directory holds data on about 14,000 axles, but
no more than 30 trains. Per train, only information on the first 1,400 axles is stored. In the
same SRAM as these directories is the Event Log, which also operates as a circular buffer.
Under the CPU on the right is a white reset button . Pressing it causes a "hard reset" of the
Processor board. As long as no train is present at the site, pressing the reset button doesn't
affect the setup information or train data. However, if a train is present, pressing the reset
button only loses train data for that train.
The Processor board requires regulated 5 VDC and regulated 12 VDC for operation. The
input power is received from the System Interface board.
Between the two CPUs is a coin-cell battery . During a power interruption to the Processor
board, this battery keeps the stored train data from being lost and the time/date accurate. If
the battery is low or dead, there is no danger of losing train data unless the power to the
system is lost. If you power down the system and remove the battery on the Processor board,
the time, the date, and all train data will be lost.