1-79
HDW-750/750CE V1
1-26. Circuit Description
1-26-9. Option Board
Picture cache board (MY-99 board : HKDW-703)
The circuit board MY-99 implements the LOOP REC and
performs the following processes.
The signal format of the compressed video data and the
audio data that are supplied from the video system circuit
of the DVP-18 board during the LOOP REC mode or the
INTERVAL REC mode, is converted at the LOOP MEM-
ORY (IC201) to be suitable for storage in the SDRAM.
The video data is then written sequentially in the SDRAM
(IC301 to IC308) and the audio data is written in the
MEMORY (IC309 and IC310). The stored data is read
from the memory in accordance with the specified timing
and returned to the original signal format by the LOOP
MEMORY (IC201) again. Then the video data passes
through the BUS SWITCH (IC202 and IC204) and the
audio data passes through the SEL (IC207) respectively,
and are sent to the video system circuit of the DVP-18
board. The TC data is handled in the same manner as the
audio data and is stored in the MEMORY (IC309 and
IC310).
Control of the read/write timings of the SDRAM is
performed by commands supplied from the I/O EXPAND-
ER (IC103). These are controlled by the system control
circuit of the SS CPU (IC1) of the SS-92 board.
Regarding the clock signal for the SDRAM, the SDRAM
(IC301 to IC308) for video data receives the 46.360 MHz
clock coming from the video system circuit of the DVP-18
board after it is phase-compensated by the CLOCK
DRIVER (IC141) of the MY-99 board. The MEMORY
(IC309 and IC310) for audio data receives the clock from
the LOOP MEMORY (IC201).
Slow shutter board (PM-22 board : HKDW-705)
The PM-22 board is mounted between the output side of
the digital-pixel-addition IC (IC1017) and the input side of
the digital process IC (IC1019) on the DCP-28B board and
processes the following:
The timing pulse output from FPGA (IC5) of the PM-22
board interrupts the CCD read out pulse which is output
from the TG-219A board. Consequently, the signal electric
charge is stored in the CCD. At the same time, this timing
pulse sets the output of the digital process IC (IC1019) on
the DCP-28B board to high impedance state.
During the storage time, the digital video signal which was
written in SDRAM (IC2, IC3) of the PM-22 board is
output to the digital process IC (IC1019), to complement
the image data.
When the timing pulse from the PM-22 board stops
interrupting the CCD read out pulse, output of the digital
process IC (IC1019) also become active, and the digital
video signal is written in SDRAM (IC2, IC3) of the PM-22
board.
By consecutively implementing the above procedures
storage and complement for the image are implemented.
R CH
CCD
G CH
CCD
B CH
CCD
BI BOARD
PA BOARD
TG BOARD
CDS
CDS
CDS
DCP BOARD
VA
AD
PIXEL-
ADDITION
DEFECTION
SYSTEM
IC1019
IC1017
IC2, IC3
SCVP
DEFCON (FPGA)
SDRAM
IC5
F_ACM
(FPGA)
PM-22 BOARD
CCD
TG
CCD READ OUT PULSE
Fig.4 Circuit description of the PM-22 board
