1-66
HDW-750/750CE V1
1-26. Circuit Description
1-26-3. Video Signal System
1-26-3. Video Signal System (DVP-18 Board)
.
Signal processing during recording
The 74.176 MHz (for HDW-750) or 74.25 MHz (for
HDW-750CE) 20-bit Y-signal and the PbPr signal that are
supplied from the camera circuit of the DCP-28 board to
the DVP-18 board, are passed through the DF.F (IC140 to
IC142) and then input to the FIL (IC160) rate converter
circuit. The 74.176 MHz (for HDW-750) or 74.25 MHz
(for HDW-750CE) 20-bit Y-signal and the PbPr signal are
down-sampled by the rate converter circuit to the 46.360
MHz (for HDW-750) or 38.672 MHz (for HDW-750CE)
20-bit multiplexed Y/PbPr signal. At the same time, the
signal is sampled by every other pixel. The output signal
from the rate converter circuit is sent to the bit rate reduc-
tion circuit of the HENC-A (IC300) and HENC-B (IC350)
via the BUS SWITCH (IC302). In the bit rate reduction
circuit, the Y-signal is grouped into the signal unit of 8
pixels (H)
x
8 pixels (V) and the PbPr signal is grouped
into the signal unit of 4 pixels (H)
x
8 pixels (V), to which
shuffling processing (i.e., the adjacent blocks are assigned
to the six segments) is implemented. After the shuffling
processing, the DCT coefficient is calculated from the data
of the respective blocks so that the quantization and VLC
(Variable Length Coding) processing are performed. The
compressed video data passes through DF.F (IC403 and
IC404) and is sent to ECC (IC400) that is the error correc-
tion encoder circuit. In the error correction encoder circuit,
the compressed picture data receives the following pro-
cesses.
.
Generation of the outer parity and inner parity
.
Addition of the SYNC/ID code
.
Generation of SYNC block
At the same time, the serial audio data that is supplied
from the audio circuit of the FP-121 board passes through
the SEL (IC406) and is input to the error correction
encoder circuit. In the error correction encoder circuit, the
serial audio data receives the processes of generating the
outer parity and inner parity, addition of the SYNC/ID
code and the SYNC block is generated. After the serial
audio data is multiplexed with the picture data, the multi-
plexed signal is sent to the RF system circuit in the EQ-88
board as two-channel serial data.
.
Signal processing during playback
The playback data that is supplied from the RF system
circuit of the EQ-88 board to the DVP-18 board, passes
through the BUS SWITCH (IC501) and CPLD (IC502),
and is input to the error correction decoder circuit of the
ADAM-S (IC500). In the error correction decoder circuit,
the errors that are occured during the recording and
playback processes are corrected. An error flag is added to
the errors that could not be corrected by the error correc-
tion decoder circuit so that error concealment can be
performed by the error concealment circuit of the CNC
(IC700). At the same time, the audio data is separated in
the error correction decoder circuit, and the separated
audio data is sent to the audio circuit of the FP-121 board
as the playback serial audio data.
The playback video data that is supplied from the error
correction decoder circuit, passes through the BUS
SWITCH (IC506 and IC507) and is sent to the bit rate
reduction decoder circuit that consists of HDEC-A (IC600)
and HDEC-B (IC650). In the bit rate reduction decoder
circuit, the reverse processing of the bit rate reduction
circuit is performed. The 46.360 MHz (for HDW-750) or
38.672 MHz (for HDW-750CE) 20-bit Y/PbPr signal is
generated by the bit rate reduction decoder circuit, and is
sent to the error concealment circuit of CNC (IC700). In
the error concealment circuit, the correct data is judged for
error data for which the error flag is set, from the peripher-
al pixels and the data of the previous frame, and the error
concealment is performed. After the error concealment, the
data passes through the BUS SWITCH (IC161) and is
input to the rate converter circuit of FIL (IC160). In the
rate converter circuit, the 46.360 MHz (for HDW-750) or
38.672 MHz (for HDW-750CE) 20-bit Y/PbPr signal is
up-sampled to the 74.176 MHz (for HDW-750) or 74.25
MHz (for HDW-750CE) 20-bit Y-signal and to the PbPr
signal, which are then sent to the camera system circuit in
the DCP-28 board.
