Schweitzer Engineering Laboratories SEL-700G Series, Instruction Manual, Page: 18 / 824

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SEL-700G Relay Instruction Manual Date Code 20170814
List of Figures
Figure 4.87 Positive-Sequence Voltage-Polarized Directional Element for Phase Overcurrent
Elements ......................................................................................................................... 4.119
Figure 4.88 Routing of Directional Elements to Negative-Sequence and Phase Overcurrent
Elements ......................................................................................................................... 4.120
Figure 4.89 Direction Forward/Reverse Logic for Negative-Sequence Overcurrent Elements ............ 4.120
Figure 4.90 Direction Forward/Reverse Logic for Phase Overcurrent Elements ........................................ 4.121
Figure 4.91 Zero-Sequence Impedance Network and Relay Polarity ................................................... 4.131
Figure 4.92 Zero-Sequence Impedance Plot for Solidly-Grounded, Mostly Inductive System ............ 4.131
Figure 4.93 Hybrid Power System With Neutral-Ground Resistor ....................................................... 4.132
Figure 4.94 Load-Encroachment Logic for X Side ............................................................................... 4.135
Figure 4.95 Load-Encroachment Logic for Y Side ............................................................................... 4.136
Figure 4.96 Three-Phase Power Elements Logic................................................................................... 4.139
Figure 4.97 Power Elements Operation in the Real/Reactive Power Plane........................................... 4.140
Figure 4.98 X-Side Over- and Underfrequency Element Logic ............................................................ 4.142
Figure 4.99 Y-Side Over- and Underfrequency Element Logic ............................................................ 4.143
Figure 4.100 81R Frequency Rate-of-Change Scheme Logic................................................................. 4.144
Figure 4.101 Undervoltage Element Logic.............................................................................................. 4.148
Figure 4.102 Overvoltage Element Logic................................................................................................ 4.149
Figure 4.103 Zero-Sequence Overvoltage Elements (59G)..................................................................... 4.150
Figure 4.104 Channel VS Voltage Elements (27S, 59S) ......................................................................... 4.150
Figure 4.105 Synchronism-Check Function Voltage Elements ............................................................... 4.155
Figure 4.106 Synchronism-Check Function Voltage Element Characteristic ......................................... 4.155
Figure 4.107 Synchronism-Check Function 25RCFX and SYNCPX/SYNCPY Setting Examples ....... 4.156
Figure 4.108 Synchronism-Check Function Slip Elements..................................................................... 4.157
Figure 4.109 Synchronism-Check Function Angle Elements ................................................................. 4.158
Figure 4.110 Breaker Close Failure Logic Diagram................................................................................ 4.158
Figure 4.111 Synchronism-Check Function Angle Characteristics ........................................................ 4.159
Figure 4.112 Synchronism-Check Voltage Window and Slip Frequency Elements................................ 4.165
Figure 4.113 Synchronism-Check Elements ........................................................................................... 4.166
Figure 4.114 Angle Difference Between VPY and VS Compensated by Breaker Close Time
(fPY < fS and VPY Shown as Reference in This Example)........................................... 4.170
Figure 4.115 Overall Functional Block Diagram .................................................................................... 4.173
Figure 4.116 Simplified Block Diagram, Frequency and Phase Matching Elements ............................. 4.175
Figure 4.117 Simplified Block Diagram, Voltage Matching Elements ................................................... 4.176
Figure 4.118 Synchroscope ..................................................................................................................... 4.177
Figure 4.119 Graphical Display of Generator Autosynchronism Report ................................................ 4.178
Figure 4.120 Loss-of-Potential Generic Logic (Applies to both X and Y Sides).................................... 4.180
Figure 4.121 Demand Current Logic Outputs ......................................................................................... 4.181
Figure 4.122 Response of Thermal and Rolling Demand Meters to a Step Input
(Setting DMTC = 15 minutes)........................................................................................ 4.182
Figure 4.123 Voltage V
S
Applied to Series RC Circuit........................................................................... 4.183
Figure 4.124 Pole Open Logic Diagram, Breaker 52X ........................................................................... 4.185
Figure 4.125 Pole Open Logic Diagram, Breaker 52Y ........................................................................... 4.186
Figure 4.126 Trip Logic........................................................................................................................... 4.188
Figure 4.127 Typical Generator Trip TR Logic (SEL-700G0, SEL-700G1, SEL-700GT)..................... 4.189
Figure 4.128 Typical Intertie Trip TR Logic (SEL-700GT).................................................................... 4.189
Figure 4.129 Typical Feeder Trip TR Logic (SEL-700GW) ................................................................... 4.190
Figure 4.130 Close Logic ........................................................................................................................ 4.191
Figure 4.131 Typical Generator or Intertie Close CL Logic (SEL-700G or GT).................................... 4.192
Figure 4.132 Typical Feeder Close CL Logic (SEL-700GW)................................................................. 4.193
Figure 4.133 Schematic Diagram of a Traditional Latching Device ....................................................... 4.194
Figure 4.134 Logic Diagram of a Latch Switch ...................................................................................... 4.194
Figure 4.135 SEL
OGIC
Control Equation Variable/Timers SV01/SV01T–SV32T ................................. 4.196
Figure 4.136 Result of Falling-Edge Operator on a Deasserting Input ................................................... 4.199
Figure 4.137 Example Use of SEL
OGIC
Variables/Timers ...................................................................... 4.200
Figure 4.138 Counter 01 .......................................................................................................................... 4.203