Schweitzer Engineering Laboratories SEL-700G Series, Instruction Manual

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4.107
Date Code 20170814 Instruction Manual SEL-700G Relay
Protection and Logic Functions
Group Settings (SET Command)
➤
If DELTAY_ := WYE, EFWDLOP := Y, internal enable DIRIE
is not asserted, and an LOP condition occurs, then the forward
logic point (Relay Word bit DIRGF) asserts to logical 1, thus
enabling the residual-ground (Figure 4.83) overcurrent elements
that are set direction forward (with settings DIR1 = F, DIR2 = F,
etc.). These direction forward overcurrent elements effectively
become non-directional and provide overcurrent protection during an
LOP condition. With the rest of the settings remaining the same, if the
internal enable DIRIE is asserted and an LOP condition occurs, then
the output of the forward/reverse logic points (Relay Word bits
DIRGF and DIRGR) is dictated by the Channel
IN current-
polarized directional element (Relay Word bits FDIRI and
RDIRI, respectively).
➤
The previous is also true for DELTAY_ := DELTA,
EFWDLOP := Y, EXT3V0_X := NONE.
➤
If DELTAY_ := DELTA, EFWDLOP := Y, EXT3V0_X := VS or
VN, internal enable DIRVE is asserted, and internal enable
DIRIE is not asserted, then the LOP condition will not cause the
forward directional outputs to assert as shown in Figure 4.81. In
this situation, the directional element enabled by DIRVE is still
able to operate reliably during an LOP condition, so there is no
need to force the forward outputs to assert. However, when
DIRVE is not asserted, a standing LOP condition will force the
forward outputs to assert continuously. Consider this when
determining residual-ground overcurrent element pickup settings
and time delay settings, so that load conditions do not cause a
forward-set ground directional overcurrent element to pickup
and start timing.
The effect of LOP on the neutral-ground directional logic is described below
(refer to Figure 4.82).
➤
If DELTAY_ := WYE, EFWDLOP := Y, and an LOP condition
occurs, then the forward logic point (Relay Word bit DIRNF)
asserts to logical 1, thus enabling the neutral-ground
(Figure 4.84) overcurrent elements that are set direction forward
(with settings DIR1 = F, DIR2 = F, etc.). These direction forward
overcurrent elements effectively become non-directional and
provide overcurrent protection during an LOP condition.
➤
If DELTAY_ := DELTA, EFWDLOP := Y, EXT3V0_X := VS or
VN, and internal enable DIRVE is asserted, then the LOP
condition will not cause the forward directional outputs to assert
as shown in Figure 4.82. In this situation, the directional element
enabled by DIRNE is still able to operate reliably during an LOP
condition, so there is no need to force the forward outputs to
assert. However, when DIRNE is not asserted, a standing LOP
condition will force the forward outputs to assert continuously.
Consider this when determining neutral-ground overcurrent
element pickup settings and time delay settings, so that load
conditions do not cause a forward-set ground directional overcurrent
element to pickup and start timing.
Direction Forward/Reverse Logic.
Refer to Figure 4.72, Figure 4.73,
Figure 4.83 and Figure 4.84.
With the forward Relay Word bits, DIRGF and DIRNF and the reverse Relay
Word bits, DIRGR and DIRNR, in Figure 4.83 and Figure 4.84, respectively,