scheider electric MiCOM P746, Technical Manual

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P746/EN FD/G31 Firmware Design
(FD) 9-
8
MiCOM P746
FD
2. HARDWARE MODULES
The relay is based on a modular hardware design where each module performs a separate
function within the relay operation. This section describes the functional operation of the
various hardware modules.
2.1 Processor board
The relay is based around a TMS320VC33 floating point, 32-bit digital signal processor
(DSP) operating at a clock frequency of 75MHz. This processor performs all of the
calculations for the relay, including the protection functions, control of the data
communication and user interfaces including the operation of the LCD, keypad and LEDs.
The processor board is located directly behind the relay’s front panel which allows the LCD,
function keys and LEDs to be mounted on the processor board along with the front panel
communication ports. These comprise the 9-pin D-connector for EIA(RS)232 serial
communications (e.g. using MiCOM S1 V2 or Studio and Courier communications) and the
25-pin D-connector relay test port for parallel communication. All serial communication is
handled using a field programmable gate array (FPGA).
All serial communication is handled using a two-channel 85C30 serial communications
controller (SCC).
The memory provided on the main processor board is split into two categories, volatile and
non-volatile; the volatile memory is fast access SRAM which is used for the storage and
execution of the processor software, and data storage as required during the processor’s
calculations. The non-volatile memory is sub-divided into 2 groups; 4MB of flash memory for
non-volatile storage of software code, present setting values, text, configuration data, latched
data signals (from control inputs, function keys, LEDs, relay outputs) and 4MB of battery
backed-up SRAM for the storage of disturbance, event, fault and maintenance record data.
2.2 Internal communication bus
The internal interconnexion bus is controlled by the main board. Via its interconnection bus
the main board controls also the IRIG-B board (if present).
This interconnection bus is based on a 64-way ribbon cable. The ribbon cable carries the
data and address bus signals in addition to control signals and all power supply lines.
Operation of the bus is driven by the main processor board that operates as a master while
all other modules within the relay are slaves.
The DSP processor has a built-in serial port that is used to read the sample data from the
serial bus. The serial bus is also carried on the 64-way ribbon cable.
The main part of the bus is a parallel link with 6 address lines for board selection, 16 data
lines and control lines. On the main controlled bus, main board drive address and control
lines.
Other parts of the buses are:
•
Power supply which are directly wired between the two interconnection buses.
•
Serial lines for rear RS485 communication. So in any way main board keeps control of
the rear RS485 communication.