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Command Reference
R&S
®
CMW500
231
User Manual 1173.9463.02 ─ 02
STATus:OPERation:TASK:A:<netw_std>:<func_grp>:XENable
<List>
STATus:OPERation:TASK:A:<netw_std>:<func_grp>:<appl>:XENable
<List>
Sets the enable mask which allows true conditions in the EVENt part of the status register
to be reported in the summary bit. If a bit is 1 in the enable register and its associated
event bit transitions to true, a positive transition will occur in the summary bit reported to
the next higher level. See also
Structure of an SCPI Status Register
For a description of the variables <netw_std>, <func_grp> and <appl> refer to
.
Parameters:
<List>
Comma separated list of mnemonics (and/or decimal numbers
between 0 and 65535) enclosed in brackets
Example:
STAT:OPER:TASK:A:GPRF:MEAS:XEN (EPS,IQR)
Set the enable mask bits corresponding to the measurements
EPSensor (bit 2) and IQRecorder (bit 3) to true.
Firmware/Software:
V2.0.10
STATus:OPERation:XESRq
<List>
STATus:OPERation:TASK:XESRq
<List>
STATus:OPERation:TASK:A:XESRq
<List>
STATus:OPERation:TASK:A:<netw_std>:XESRq
<List>
STATus:OPERation:TASK:A:<netw_std>:<func_grp>:XESRq
<List>
STATus:OPERation:TASK:A:<netw_std>:<func_grp>:<appl>:XESRq
<List>
Sets the enable mask for the register according to the specified list. Also sets the relevant
bit in the enable mask of all higher registers up to the STATus:OPERation register and
the SRE. Thus the entire reporting path from the register up to the SRE is enabled so
that an SRQ can be generated.
If an empty list is specified (set enable mask to 0), the higher registers are not modified.
For a description of the variables <netw_std>, <func_grp> and <appl> refer to
.
Parameters:
<List>
Comma separated list of mnemonics (and/or decimal numbers
between 0 and 65535) enclosed in brackets
Example:
STAT:OPER:TASK:A:GPRF:MEAS:POW:XESRq (RUN)
Sets the RUN bit (bit 2) and disables all other bits in the ENABle
part of the following status register:
STAT:OPER:TASK:A:GPRF:MEAS:POW
Also sets the relevant bit in the ENABle part of the following status
registers, without changing the other bits of these ENABle parts:
STAT:OPER:TASK:A:GPRF:MEAS: set POW bit
STAT:OPER:TASK:A:GPRF: set MEAS1 bit
STAT:OPER:TASK:A: set GPRF bit
STAT:OPER:TASK: set A bit
STAT:OPER: set TASK bit
SRE: set OPER bit
Firmware/Software:
V2.0.10
Instrument-Control Commands