Renesas PFESiP/V850EP1 User Manual Download Page 53

Page: 53 / 61

User's Manual A19069EJ2V0UM

CHAPTER 2 INTERNAL SSCG-PLL CHARACTERISTICS

The SSCG-PLL incorporated in PFESiP/V850EP1 is a spread spectrum clock generator used to suppress noise,

and is effective in reducing the peak value of electromagnetic interference (EMI) noise.

2.1 Block Diagram

Figure 2-1. SSCG-PLL Block Diagram

Standby
Control
Circuit

XT1 (input)

Oscillator

Block

XT2 (

−

)

PLL0-PLL6 (input)

PLL10-PLL11 (input)
PLL17-PLL18 (input)

Divider

PFD

Charge

Pump

+LFP

VCO

Divider

Modulation Block

M0-M6

N0-N2

P0-P1

S0-S1

PLL12-PLL13 (input)
PLL14-PLL16 (input)

SSMDL0-SSMDL1

SSADJ0-SSADJ2

TEST

Circuit

MODE

FO (output)

PLL7-PLL9 (input)

Decoder

Summary of Contents for PFESiP/V850EP1

Page 1: ...ok over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electron...

Page 2: ...t for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas...

Page 3: ...User s Manual PFESiP V850EP1 32 bit Microcontroller Dedicated to PFESiP EP 1 Document No A19069EJ2V0UM00 2nd Edition Date published September 2009 NS 2008 Product Data...

Page 4: ...User s Manual A19069EJ2V0UM 2 MEMO...

Page 5: ...including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken...

Page 6: ...on NEC Electronics products are not taken measures to prevent radioactive rays in the product design When customers use NEC Electronics products with their products customers shall on their own respon...

Page 7: ...8 Input Clock Timing p 17 Modification of 1 7 1 2 Output Clock The mark R shows major revised points The revised points can be easily searched by copying an R in the PDF file and specifying it in the...

Page 8: ...s of this manual have general knowledge of electricity logic circuits microcontrollers SRAM Page ROM and SDRAM Conventions Data significance Higher digits on the left and lower digits on the right Act...

Page 9: ...re CPU Function User s Manual A19070E PFESiP V850EP1 Hardware USB Function User s Manual A19071E PFESiP V850EP1 Hardware USB Function Sample Software Application Note A19349E Documents related to PFES...

Page 10: ...CSI interface pins 44 1 7 9 N Wire interface pins 47 1 8 A D Converter Characteristics 49 1 9 Power Supply Application Interruption Procedure 50 1 9 1 Input buffer 50 1 9 2 Output buffer bidirectiona...

Page 11: ...33 1 14 Read Timing SRAM External ROM External I O 34 1 15 Write Timing SRAM External ROM External I O 35 1 16 DMA Flyby Transfer Timing SRAM External I O 36 1 17 DMA Flyby Transfer Timing External I...

Page 12: ...ng 30 1 15 Access Timing SRAM External ROM External I O 32 1 16 Bus Hold Timing 39 1 17 BUSCLK synchronization Signal 41 1 18 SBUSCLK synchronization Signal 42 1 19 External Bus Reset Output Pin 43 1...

Page 13: ...of voltages for normal logical operation when VSS 0 V High level input voltage VIH For voltage applied to the input of PFESiP V850EP1 this value indicates the voltage of the high level state in which...

Page 14: ...ge when the output is at high impedance Output short circuit current IOS Current that flows out if the output pin is short circuited to GND when output is at the high level Input leakage current ILI C...

Page 15: ...Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the ve...

Page 16: ...Atype TDOPAC33xx12 12 0 mA High level output current 3 3 V buffer IOH VOH 2 4 V 18 mAtype TDOPAC33xx18 18 0 mA Low level output voltage VOL IOL 0 mA 3 3 V buffer 0 1 V High level output voltage VOH IO...

Page 17: ...the operation is guaranteed 1 When turning on power Set to no more than 100 ms the time from when the level of the power supply that starts first becomes 0 1VDD until the level of the power supply tha...

Page 18: ...1 Input clock Table 1 8 Input Clock Timing Parameter Symbol Conditions MIN MAX Unit X1 input cycle tSCLK 20 83 ns PCLKIN input frequency fSPCLK 25 33 ns DCK input cycle tSDCK 40 ns UCLK input frequen...

Page 19: ...rise time tKR1 3 3 ns BUSCLK fall time tKF1 3 3 ns SBUSCLK high level width tWSKH1 0 5T 2 1 0 5T 2 1 ns SBUSCLK low level width tWSKL1 0 5T 2 1 0 5T 2 1 ns SBUSCLK rise time tSKR1 1 85 ns SBUSCLK fal...

Page 20: ...A19069EJ2V0UM 18 3 Reset timing Table 1 10 Reset Timing Parameter Symbol Conditions MIN MAX Unit RESET pin low level width tWRSL 400 ns Caution Sufficiently evaluate the oscillation stabilization tim...

Page 21: ...l memories 2 The electrical specifications of the external pins of the PFESiP V850EP1 are calculated under fixed load conditions In an application design using the PFESiP V850EP1 these load conditions...

Page 22: ...Z7 output BCYSTZ output RDZ IORDZ output read WRZ0 WRZ3 WRSTBZ IOWRZ output write D0 D31 I O read WAITZ input D0 D31 I O write tDKWRH T1 TW T2 tDKA tDKA tDKBSL tDKBSH tDKBSL tDKRDH tDKRDL tDKRDH tDKRD...

Page 23: ...ut D0 D31 I O WAITZ input BCYSTZ output TASW T1 TW T2 TI tDKRDH tDKWRH tDKRDL tHKOD tSKID tHKID tHKW tSKW tHKW tSKW tDKBSL tDKBSH tDKBSL tDKA Note tDKA tDKRDH tDKRDL Note In the case of CSZ0 CSZ7 Rema...

Page 24: ...put D0 D31 I O WAITZ input BCYSTZ output TASW T1 TW T2 TI tDKRDH tDKWRH tDKWRL tDKOD tHKW tSKW tHKW tSKW tDKBSL tDKBSH tDKBSL tDKA Note tDKA tDKWRH tDKWRL tDKRDL tHKOD Note In the case of CSZ0 CSZ7 Re...

Page 25: ...output TASW T1 TW T2 TI tDKRDH tDKWRH tDKWRL tHKW tSKW tHKW tSKW tDKBSL tDKBSH tDKBSL tDKA Note tDKA tDKWRH tHKOD TF tDKRDL tDKRDH WRZ0 WRZ3 WRSTBZ output tDKWRH IORDZ output tDKRDH Note In the case...

Page 26: ...ut BCYSTZ output TASW T1 TW T2 TI tDKRDH tHKW tSKW tHKW tSKW tDKBSL tDKBSH tDKBSL tDKA Note tDKA tHKOD TF tDKRDL tDKRDH WRZ0 WRZ3 WRSTBZ output tDKWRH IOWRZ output tDKWRH tDKWRL tDKWRH tDKRDH Note In...

Page 27: ...KBSH BUSCLK output A0 A25 output WRZ0 WRZ3 WRSTBZ output RDZ output D0 D31 I O WAITZ input BCYSTZ output CSZ0 CSZ7 output tDKA tDKA tDKA tDKA tDKRDH tHKID tSKID tHKW tSKW tHKW tSKW Remarks 1 Timing wh...

Page 28: ...LK tDKRAS 1 5 11 0 ns SDCASZ delay time from BUSCLK tDKCAS 1 5 11 0 ns SDWEZ delay time from BUSCLK tDKWE 1 5 11 0 ns DQM0 DQM3 delay time from BUSCLK tDKDQM 1 5 11 0 ns SDCKE delay time from BUSCLK t...

Page 29: ...put BCYSTZ output CSZnNote output SDRASZ output SDCASZ output SDWEZ output DQM0 DQM3 output D0 D31 I O SDCKE output tDKA tDKBC tDKCS tDKRAS tDKRAS tDKCAS tDKCAS tDKWE tDKDQM tDKDQM tHKDRM tSKDRM tDKCK...

Page 30: ...S tDKCS tDKRAS tDKRAS tDKCAS tDKCAS tDKWE tDKDQM tDKWE tDKDQM tDKDT1 tDKDT2 tDKDT2 tDKDT2 tHZKDT BUSCLK output A0 A25 output BCYSTZ output CSZnNote output SDRASZ output SDCASZ output SDWEZ output DQM0...

Page 31: ...ng SDRAM Access TRPW ALLPRE REFW REFW TREF REFW tDKCS tDKCS tDKRAS tDKRAS tDKCAS tDKWE tDKCS tDKCS tDKRAS tDKRAS tDKCAS tDKWE tDKREF tDKREF REFW TRPW TRPW TRPW H BUSCLK output A0 A25 output REFRQZ out...

Page 32: ...SCLK tHKHR 2 0 ns Delay time from BUSCLK to HLDAKZ tDKHA 1 5 11 0 ns HLDRQZ high level width tWHQH 5 8 tBCLK ns HLDAKZ low level width tWHAL 9 5 tBCLK ns Delay time from BUSCLK to bus float tDKCF 1 5...

Page 33: ...output HLDRQZ input HLDAKZ output A0 A25 output D0 D31 I O CSZ0 CSZ7 output BCYSTZ output RDZ output WRZ0 WRZ3 WRSTBZ output WAITZ input Address Data Undefined tSHRK tHKHR tSHRK tHKHR tSHRK tWHQH tDH...

Page 34: ...ns SRDZ SIORDZ delay time from SBUSCLK tDKRDH 1 5 11 0 ns SWRZ0 to SWRZ1 SWRSTBZ SIOWRZ from SBUSCLK tDKWRL 1 5 11 0 ns SWRZ0 to SWRZ1 SWRSTBZ SIOWRZ from SBUSCLK tDKWRH 1 5 11 0 ns SBCYSTZ delay time...

Page 35: ...CSZ3 output SBCYSTZ output SRDZ SIORDZ output read SWRZ0 SWRZ1 SWRSTBZ SIOWRZ output write SD0 SD15 I O read SWAITZ input SD0 SD15 I O write tDKWRH T1 TW T2 tDKA tDKA tDKBSL tDKBSH tDKBSL tDKRDH tDKRD...

Page 36: ...utput SD0 SD15 I O SWAITZ input SBCYSTZ output TASW T1 TW T2 TI tDKRDH tDKWRH tDKRDL tHKOD tSKID tHKID tHKW tSKW tHKW tSKW tDKBSL tDKBSH tDKBSL tDKA Note tDKA tDKRDH tDKRDL Note In the case of SCSZ0 S...

Page 37: ...utput SD0 SD15 I O SWAITZ input SBCYSTZ output TASW T1 TW T2 TI tDKRDH tDKWRH tDKWRL tDKOD tHKW tSKW tHKW tSKW tDKBSL tDKBSH tDKBSL tDKA Note tDKA tDKWRH tDKWRL tDKRDL tHKOD Note In the case of SCSZ0...

Page 38: ...STZ output TASW T1 TW T2 TI tDKRDH tDKWRH tDKWRL tHKW tSKW tHKW tSKW tDKBSL tDKBSH tDKBSL tDKA Note tDKA tDKWRH tHKOD TF tDKRDL tDKRDH SWRZ0 SWRZ1 SWRSTBZ output tDKWRH SIORDZ output tDKRDH Note In th...

Page 39: ...nput SBCYSTZ output TASW T1 TW T2 TI tDKRDH tHKW tSKW tHKW tSKW tDKBSL tDKBSH tDKBSL tDKA Note tDKA tHKOD TF tDKRDL tDKRDH SWRZ0 SWRZ1 SWRSTBZ output tDKWRH SIOWRZ output tDKWRH tDKWRL tDKWRH tDKRDH N...

Page 40: ...BUSCLK output SA0 SA20 output SWRZ0 SWRZ1 SWRSTBZ output SRDZ output SD0 SD15 I O SWAITZ input SBCYSTZ output SCSZ0 SCSZ3 output tDKA tDKA tDKA tDKA tDKRDH tHKID tSKID tHKW tSKW tHKW tSKW Remarks 1 Ti...

Page 41: ...tHKHR 2 0 ns Delay time from SBUSCLK to SHLDAKZ tDKHA 1 5 11 0 ns SHLDRQZ high level width tWHQH 5 8 tBCLK ns SHLDAKZ low level width tWHAL 9 5 tBCLK ns Delay time from SBUSCLK to bus float tDKCF 1 5...

Page 42: ...SHLDRQZ input SHLDAKZ output SA0 SA20 output SD0 SD15 I O SCSZ0 SCSZ3 output SBCYSTZ output SRDZ output SWRZ0 SWRZ1 SWRSTBZ output SWAITZ input Address Data Unidentified tSHRK tHKHR tSHRK tHKHR tSHRK...

Page 43: ...2 from BUSCLK tHKDR2 4 3 m tBCLK 4 3 ns DMAAKZ0 DMAAKZ3 output delay time from BUSCLK tDKDA 2 0 11 0 ns DMAAKZ0 DMAAKZ3 low level width tWDAL 9 0 n tBCLK 9 0 n tBCLK ns TCZ0 TCZ3 output delay time fr...

Page 44: ...hold time 2 from SBUSCLK tHKDR2 4 3 m tBCLK 4 3 ns SDMAAKZ0 SDMAAKZ3 output delay time from SBUSCLK tDKDA 2 0 11 0 ns SDMAAKZ0 SDMAAKZ3 low level width tWDAL 9 0 n tBCLK 9 0 n tBCLK ns STCZ0 STCZ3 out...

Page 45: ...e from VBCLKOUT tDVBRESZ 1 0 10 0 ns Figure 1 22 External Bus Reset Output Pin VBCLKOUT output VBRESTOZ output tDVBRESZ 2 SiP internal connection bus interface pins The access timing of the SiP intern...

Page 46: ...0 ns Sin input hold time to SCKn tHSI 2 0 ns SOn output delay time to SCKn tDSO 6 0 ns SOn output delay time from SCKn tDSO 6 0 ns SOn output hold time from SCKn tHSO tCSICYC 1 2 1 5 ns SOn output ho...

Page 47: ...00 SCKnNote output SOnNote output SInNote input tDSO tHSO tSSI tHSI tCSICYC Note n 0 1 Remark Broken lines indicate high impedance Figure 1 25 CSI Access Timing CKP DAP 01 SCKnNote output SOnNote out...

Page 48: ...0 SCKn Note output SOn Note output SIn Note input tDSO tHSO tSSI tHSI tCSICYC Note n 0 1 Remark Broken lines indicate high impedance Figure 1 27 CSI Access Timing CKP DAP 11 SCKnNote output SOn Note I...

Page 49: ...LK Note tDTRCEND 0 0 tCCLK 0 5 3 5 ns Note The data output timing of TRCDATA0 TRCDATA7 or TRCEND can be output at the both rising and falling edges of TRCCLK It also can be output at the falling edge...

Page 50: ...rial Interface Parameter Symbol MIN MAX Unit DMS input setup time to DCK tSDMS 10 0 ns DMS input hold time from DCK tHDMS 20 0 ns DDI input setup time to DCK tSDDI 10 0 ns DDI input hold time from DCK...

Page 51: ...Note 3 4 LSB Analog input voltage VWASN AVREFM AVREFP V AVDD power supply current AIDD 10 mA ADTRG high level width tWAIH 500 ns ADTRG low level width tWAIL 500 ns Notes 1 Excluding quantization error...

Page 52: ...ormula Pin capacitance CT interface block capacitance CB capacitance CP of each package 1 9 1 Input buffer Table 1 27 Capacitance of Interface Block CB Interface Level CB MIN CB MAX 3 3 V 2 0 pF 4 0 p...

Page 53: ...ak value of electromagnetic interference EMI noise 2 1 Block Diagram Figure 2 1 SSCG PLL Block Diagram Standby Control Circuit XT1 input Oscillator Block XT2 PLL0 PLL6 input PLL10 PLL11 input PLL17 PL...

Page 54: ...Frequency fout fout fstd n m p 25 200 MHz Output Duty duty 47 53 CL 0 2pF Output Period Jitter tpj 150 150 Ps Fixed frequency mode Multiple Rate MULT MULT n m p 0 182 50 PLL13 PLL12 SSMDL1 SSMDL0 00 2...

Page 55: ...n m 100 200 MHz Output Frequency fout fout fstd n m p 25 200 MHz Input Duty Iduty 30 70 Multiple Rate MULT MULT n m p 0 182 50 PLL0 PLL6 PLL7 PLL9 PLL10 PLL11 PLLM0 PLLM6 PLLN0 PLLN2 PLLP0 PLLP1 Setti...

Page 56: ...3 to 100 p 2 PLLP0 to PLLP1 setting value 1 2 4 Multiple rate n m p The following specifications are satisfied in AAPLSCGH Table 2 1 PLL Operating Conditions Parameter Symbol Formula MIN MAX Unit Inpu...

Page 57: ...o SSADJ2 dither range mode input Set SSCG output frequency modulation rate These pins are connected to ADJ0 to ADJ2 of AAPLSCGH If SSADJ2 1 and SSADJ1 1 the mode with no frequency modulation occurs Ta...

Page 58: ...1 45 fpfd 1 70 1 1 1 70 fpfd 2 00 2 3 5 PLLFOEN PLL FO output enable input The FO output of the internal PLL can be output from the PLLFO pin The IDLE control circuit is not stopped even in the IDLE...

Page 59: ...of traces 8 ID850QB Note 3 NECElectronicsCorporation QB V850MINI NECElectronicsCorporation MINI CUBE No trace function RX850pro NECElectronicsCorporation CA850 NECElectronicsCorporation PARTNER Note 4...

Page 60: ...User s Manual A19069EJ2V0UM 58 MEMO...

Page 61: ...02 8175 9600 http www tw necel com NEC Electronics Singapore Pte Ltd 238A Thomson Road 12 08 Novena Square Singapore 307684 Tel 6253 8311 http www sg necel com NEC Electronics Korea Ltd 11F Samik Lav...

Search results

Summary of Contents for PFESiP/V850EP1

Reviews:

Related manuals for PFESiP/V850EP1

Brands by name

Popular brands

Renesas PFESiP/V850EP1, User Manual

Search results

Summary of Contents for PFESiP/V850EP1

Reviews:

Related manuals for PFESiP/V850EP1

Brands by name

Popular brands