CHAPTER 2 INTERNAL SSCG-PLL CHARACTERISTICS
User's Manual A19069EJ2V0UM
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2.3.2 SSMDL0 to SSMDL1 (modulation frequency range) (input)
Set SSCG-output modulation period.
These pins are directly connected to MDL0 and MDL1 of AAPLSCGH.
Table 2-2. Setting SSCG-output Modulation Period by SSMDL0 to SSMDL1
PLL13 PLL12
SSMDL1 SSMDL0
Modulation Period [kHz]
0
0
15.00 to 26.25 (open)
0
1
25.00 to 36.75
1
0
35.00 to 48.30
1
1
45.00 to 68.25
2.3.3 SSADJ0 to SSADJ2 (dither range / mode) (input)
Set SSCG-output frequency modulation rate.
These pins are connected to ADJ0 to ADJ2 of AAPLSCGH.
If SSADJ2
=
1 and SSADJ1
=
1, the mode with no frequency modulation occurs.
Table 2-3. Setting SSCG-output Frequency Modulation Rate
PLL16 PLL15 PLL14
SSADJ2 SSADJ1 SSADJ0
Frequency Modulation Rate
0 0 0
Approx.
−
0.5 %
0 0 1
Approx.
−
1.0 %
0 1 0
Approx.
−
2.0 %
0 1 1
Approx.
−
3.0 %
1 0 0
Approx.
−
4.0 %
1 0 1
Approx.
−
5.0 %
1 1 0
No
modulation
1 1 1
No
modulation
Caution
Setting modulation affects the UART baud rate and timer interval time.
For example, with UART, evaluate the permissible baud rate error with the other party of
communication.
