CHAPTER 1 PRODUCT SPECIFCATIONS
User's Manual A19069EJ2V0UM
32
1.7.4 SiP
internal-connection bus interface pins
(1) Access timing (SRAM, external ROM, external I/O)
Table 1-15. Access Timing (SRAM, External ROM, External I/O)
Parameter Symbol
MIN.
MAX.
Unit
Address, SCSZ0-SCSZ3 output delay time (from SBUSCLK
↑
) t
DKA
1.5
11.0
ns
SRDZ, SIORDZ
↓
delay time (from SBUSCLK
↓
) t
DKRDL
1.5
11.0
ns
SRDZ, SIORDZ
↑
delay time (from SBUSCLK
↑
) t
DKRDH
1.5
11.0
ns
SWRZ0 to SWRZ1, SWRSTBZ, SIOWRZ
↓
(from SBUSCLK
↓
) t
DKWRL
1.5
11.0
ns
SWRZ0 to SWRZ1, SWRSTBZ, SIOWRZ
↑
(
from SBUSCLK
↓
) t
DKWRH
1.5
11.0
ns
SBCYSTZ
↓
delay time (from SBUSCLK
↑
) t
DKBSL
1.5
8.0
ns
SBCYSTZ
↑
delay time (from SBUSCLK
↑
) t
DKBSH
1.5
8.0
ns
SWAITZ setup time (to SBUSCLK
↑)
t
SKW
3.0
−
ns
SWAITZ hold time (from SBUSCLK
↑
) t
HKW
1.0
−
ns
Data input setup time (to SBUSCLK
↑
) t
SKID
3.0
−
ns
Data input hold time (from SBUSCLK
↑
) t
HKID
2.0
−
ns
Data output delay time (from SBUSCLK
↑
) t
DKOD
1.5
11.0
ns
Data float delay time (from SBUSCLK
↑
) t
HKOD
1.5
11.0
ns
