CHAPTER 2 INTERNAL SSCG-PLL CHARACTERISTICS
User's Manual A19069EJ2V0UM
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2.3.4 PLLS0 to PLLS1 (S-selector) (input)
Set the S-selector as below, according to the value of the PFD
input frequency (fpfd) specified in Table 2-1 when
these pins are used in frequency diffusion mode.
Table 2-4. Setting the S-selector
PLL18 PLL17
PLLS1 PLLS0
PFD Input Frequency [MHz]
0 0
1.00
≤
f
pfd
<
1.20 (Open)
0 1
1.20
≤
f
pfd
<
1.45
1 0
1.45
≤
f
pfd
<
1.70
1 1
1.70
≤
f
pfd
≤
2.00
2.3.5 PLLFOEN (PLL FO output enable) (input)
The FO output of the internal PLL can be output from the PLLFO pin.
The IDLE control circuit is not stopped even in the IDLE mode, because it is on the CPU side.
FO is output to PLLFO only when a high level is input to PLLFOEN.
A low level is output when a low level is input to PLLFOEN.
This output control is an enable control configuration. Noise (whiskers) may occur when switching is performed
during an operation.
Table 2-5. PLL FO Output Control by PLLFOEN Pin
PLLFOEN
PLL FO Output Control
0 Low-level
output
1 Output
enabled
