CHAPTER 1 PRODUCT SPECIFCATIONS
User's Manual A19069EJ2V0UM
20
(a) Access timing (SRAM, external ROM, external I/O)
Figure 1-3. Access Timing (SRAM, External ROM, External I/O)
BUSCLK (output)
A0-A25, CSZ0-CSZ7 (output)
BCYSTZ (output)
RDZ, IORDZ (output)
(read)
WRZ0-WRZ3, WRSTBZ, IOWRZ
(output) (write)
D0-D31 (I/O)
(read)
WAITZ (input)
D0-D31 (I/O)
(write)
< t
DKWRH
>
T1 TW
T2
< t
DKA
>
< t
DKA
>
<t
DKBSL
> <t
DKBSH
> <
t
DKBSL
>
<t
DKRDH
>
<t
DKRDL
>
< t
DKRDH
>
< t
DKRDL
>
< t
DKWRL
>
< t
DKWRL
>
< t
DKWRH
>
< t
HKOD
>
< t
SKID
>
< t
HKID
>
< t
DKOD
>
< t
HKOD
>
< t
SKW
>
< t
HKW
>
< t
HKW
>
< t
SKW
>
Remarks 1.
Timing when the number of waits set by the DWC0 and DWC1 registers is 0.
2.
Broken lines indicate high impedance.
