CHAPTER 1 PRODUCT SPECIFCATIONS
User's Manual A19069EJ2V0UM
33
(a) Base access timing (SRAM, external ROM, external I/O)
Figure 1-13. Base Access Timing (SRAM, External ROM, External I/O)
SBUSCLK (output)
SA0-SA20, SCSZ0-SCSZ3 (output)
SBCYSTZ (output)
SRDZ, SIORDZ (output) (read)
SWRZ0-SWRZ1, SWRSTBZ, SIOWRZ
(output) (write)
SD0-SD15 (I/O) (read)
SWAITZ (input)
SD0-SD15 (I/O) (write)
< t
DKWRH
>
T1 TW
T2
<t
DKA
>
< t
DKA
>
<t
DKBSL
>
<t
D KBSH
>
< t
DKBSL
>
<t
DKRDH
>
<t
DKRDL
>
< t
DKRDH
>
< t
DKRDL
>
< t
DKWRL
>
< t
DKWRL
>
< t
DKWRH
>
< t
HKOD
>
< t
SKID
>
< t
HKID
>
< t
DKOD
>
< t
HKOD
>
< t
SKW
>
< t
HKW
>
< t
HKW
>
< t
SKW
>
Remarks 1.
Timing when the number of waits set by the DWC0 and DWC1 registers is 0.
2.
Broken lines indicate high impedance.
