CHAPTER 1 PRODUCT SPECIFCATIONS
User's Manual A19069EJ2V0UM
44
1.7.8 CSI interface pins
The access timing of CSI (Clock-synchronized Serial Interface) is shown below.
CSI has a master mode and a slave mode, and they show their respective timings. The operating timing varies
depending on CKP and DAP settings.
Table 1-21. CSI Access Timing (Master Mode)
Parameter Symbol MIN.
MAX. Unit
SCKn output cycle
t
CSICYC
40.0
−
ns
Sin input setup time (to SCKn
↑
) t
SSI
14.0
−
ns
Sin input setup time (from SCKn
↓
t
SSI
14.0
−
ns
Sin input hold time (from SCKn
↑
) t
HSI
2.0
−
ns
Sin input hold time (to SCKn
↓
) t
HSI
2.0
−
ns
SOn output delay time(to SCKn
↑
) t
DSO
−
6.0 ns
SOn output delay time (from SCKn
↓
) t
DSO
−
6.0 ns
SOn output hold time (from SCKn
↓
) t
HSO
t
CSICYC
×
1/2
−
1.5
−
ns
SOn output hold time (to SCKn
↓
) t
HSO
t
CSICYC
×
1/2
−
1.5
−
ns
Remark
n
=
0, 1
Table 1-22. CSI Access Timing (Slave Mode)
Parameter Symbol MIN.
MAX. Unit
SCKn output cycle
t
CSICYC
40.0
−
ns
Sin input setup time (to SCKn
↑
) t
SSI
2.0
−
ns
Sin input setup time (from SCKn
↓
t
SSI
2.0
−
ns
Sin input hold time (from SCKn
↑
) t
HSI
2.0
−
ns
Sin input hold time (to SCKn
↓
) t
HSI
2.0
−
ns
SOn output delay time(to SCKn
↑
) t
DSO
−
15.0 ns
SOn output delay time (from SCKn
↓
) t
DSO
−
15.0 ns
SOn output hold time (from SCKn
↓
) t
HSO
t
CSICYC
×
1/2
+
2.5
−
ns
SOn output hold time (to SCKn
↓
) t
HSO
t
CSICYC
×
1/2
+
2.5
−
ns
Remark
n
=
0, 1
