CHAPTER 1 PRODUCT SPECIFCATIONS
User's Manual A19069EJ2V0UM
47
1.7.9 N-Wire interface
pins
(1) Trace interface
The access timing of the trace interface is shown below.
Table 1-23. Trace Interface
Parameter Symbol
MIN. MAX.
Unit
TRCDATA output delay time (from TRCCLK
↑
)
Note
t
DTRCDATA
0.0
t
CCLK
×
0.5
+
3.5
ns
TRCEND output delay time (from TRCCLK
↑
)
Note
t
DTRCEND
0.0
t
CCLK
×
0.5
+
3.5
ns
Note
The data output timing of TRCDATA0-TRCDATA7 or TRCEND can be output at the both rising and falling
edges of TRCCLK. It also can be output at the falling edge of TRCCLK. When the timing is output at the
falling edge of TRCCLK, each output delay time is the same as that of the timing output at the rising edge of
TRCCLK. However, the TRCCLK edge for reference differs.
Remark
t
CCLK
:
CPCLK cycle
Figure 1-28. Trace Interface
TRCCLK (output)
TRCEND (output)
TRCDATA0-
TRCDATA7 (output)
< t
DTRCDATA
>
< t
DTRCEND
>
