CHAPTER 1 PRODUCT SPECIFCATIONS
User's Manual A19069EJ2V0UM
41
1.7.5 DMA
interface pins
(3) BUSCLK-synchronization signal
The second DMA transfer request disable timing in single transfer is described below.
Table 1-17. BUSCLK-synchronization Signal
Parameter Symbol
MIN.
MAX.
Unit
DMARQZ0-DMARQZ3 setup time(from BUSCLK
↑
) t
SDRK
4.3
−
ns
DMARQZ0-DMARQZ3 hold time 1
t
HKDR1
To
DMAAKZ
↓
−
ns
DMARQZ0-DMARQZ3 hold time 2 (from BUSCLK
↑
) t
HKDR2
−
4.3 m
×
t
BCLK
−
4.3
ns
DMAAKZ0-DMAAKZ3 output delay time (from BUSCLK
↑
) t
DKDA
2.0
11.0
ns
DMAAKZ0-DMAAKZ3 low level width
t
WDAL
−
9.0
+
n
×
t
BCLK
9.0
+
n
×
t
BCLK
ns
TCZ0-TCZ3 output delay time (from BUSCLK
↑
) t
DKTC
2.0
11.0
ns
Remarks 1.
t
BCLK
:
BUSCLK cycle
2.
m
=
0 to 15 (DMARQZ0 to DMARQZ3 signal mask widths set via DMAIFC0 to DMAIFC3 registers)
3.
n
=
1 to 16 (DMAAKZ0 to DMAAKZ3 signal active-level widths set via DMAIFC0 to DMAIFC3 registers)
Figure 1-20. DMA Interface (BUSCLK-synchronization Signal)
BUSCLK (output)
DMARQZn (input)
DMAAKZn (output)
< t
HKDR2
>
TCZn (output)
< t
DKTC
>
< t
DKDA
>
< t
WDAL
>
< t
HKDR1
>
< t
SDRK
>
Remark
n
=
0-3
