CHAPTER 2 INTERNAL SSCG-PLL CHARACTERISTICS
User's Manual A19069EJ2V0UM
54
2.3.1 PLLM0-PLLM6, PLLN0-PLLN2, PLLP0-PLLP1 (PLLM, N, P-counter select)
These pins set the multiplication factor of an internal PLL.
PLLM0 to PLLM6, and PLLP0 and PLLP1 are directly connected to AAPLSCGH of the internal PLL.
PLLN0 to PLLN2 are connected to AAPLSCGH, while 92 is added to them, because the input range of AAPLSCGH
is 92 to 99 in decimal form.
The multiple rates are calculated by the following formula:
m
=
PLLM0
to PLLM6
setting value (0
to 127) + 1
: 2 to 128
n
=
PLLN0
to PLLN2
setting value (0
to 7) + 92 + 1 : 93
to 100
p
=
2
PLLP0
to PLLP1
setting value
: 1, 2, 4
Multiple rate = n/m/p
The following specifications are satisfied in AAPLSCGH.
Table 2-1. PLL Operating Conditions
Parameter Symbol
Formula
MIN.
MAX Unit
Input Frequency
f
std
−
2.0 200
MHz
PFD Input Frequency
f
pfd
f
pfd
=
f
std
/ m
1.0
2.0
MHz
VCO Output Frequency
f
vco
f
vco
=
f
std
×
n / m
100
200
MHz
Output Frequency
f
out
f
out
=
f
std
×
n / m / p
25
200
MHz
Input Duty
I
duty
−
30 70
%
multiple rate
MULT
MULT
=
n / m / p
0.182
50
−
PLL11 PLL10
PLLP1 PLLP0
p
PLL Output Frequency [MHz]
0
0
1
100 to 200
0
1
2
50 to 100
1
0
4
25 to 50
1
1
Through mode
Through mode
Furthermore, when PLLM0 to PLLM6 are all set to low level, and PLLP0 and PLLP1 are both set to high level, these
low- and high-level settings being prohibited, both of these PLL settings are set to through mode.
