Renesas PFESiP/V850EP1, User Manual

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CHAPTER 1 PRODUCT SPECIFCATIONS
User's Manual A19069EJ2V0UM
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1.7.2 Cautions on maximum operating frequency
The maximum operating frequency of PFESiP/V850EP1 varies depending on the operating conditions.
Furthermore, CPCLK, VBCLK, and BUSCLK are related as integral multiples, and VBCLK has an additional
condition to be one-half or less than CPCLK. The combinations of clock settings are therefore restricted as follows.
Table 1-11. PFESiP/V850EP1 Maximum Operating Frequency on Operating Conditions
Clock SDRAM,
Low-speed Mask ROM
Priority clock
CPCLK VBCLK BUSCLK
None CPCLK, VBCLK 200 MHz
Note
100 MHz 100 MHz
CPCLK, VBCLK 200 MHz 100 MHz 50 MHz
Note
Yes
BUSCLK 200 MHz 66.6 MHz 66.6 MHz
Note
Note This clock assigns the reference of the frequency.
Cautions 1. When performing SiP development by using the PFESiP/V850EP1, the design guarantee
values of the PFESiP/V850EP1 may not be achieved, particularly for the maximum operation
frequency, due to the SiP internal wiring and the load caused by external memories.
2. The electrical specifications of the external pins of the PFESiP/V850EP1 are calculated under
fixed load conditions. In an application design using the PFESiP/V850EP1, these load
conditions may be exceeded, depending on the configuration of external circuits. In such a
case, the electrical specifications will be inferior to those of the PFESiP/V850EP1 by itself.
1.7.3 External memory interface pins
(1) Access Timing (SRAM, external ROM, external I/O)
Table 1-12. Access Timing (SRAM, External ROM, External I/O)
Parameter Symbol MIN. MAX. Unit
Address, CSZ0-CSZ7 output delay time (from BUSCLK
↑
) t
DKA
1.5 11.0 ns
RDZ, IORDZ
↓
delay time (from BUSCLK
↓
) t
DKRDL
1.5 11.0 ns
RDZ, IORDZ ↑ delay time (from BUSCLK ↑ ) t
DKRDH
1.5 11.0 ns
WRZ0-WRZ3, WRSTBZ, IOWRZ
↓
(from BUSCLK
↓
) t
DKWRL
1.5 11.0 ns
WRZ0-WRZ3, WRSTBZ, IOWRZ
↑
( from BUSCLK
↓
) t
DKWRH
1.5 11.0 ns
BCYSTZ ↓ delay time (from BUSCLK ↑ ) t
DKBSL
1.5 9.0 ns
BCYSTZ
↑
delay time (from BUSCLK
↑
) t
DKBSH
1.5 9.0 ns
WAITZ setup time (to BUSCLK
↑
) t
SKW
3.0
−
ns
WAITZ hold time (from BUSCLK ↑ ) t
HKW
1.0 − ns
Data input setup time (to BUSCLK
↑
) t
SKID
3.8
−
ns
Data input hold time (from BUSCLK
↑
) t
HKID
1.0
−
ns
Data output delay time (from BUSCLK ↑ ) t
DKOD
1.5 11.0 ns
Data float delay time (from BUSCLK
↑
) t
HKOD
1.5 11.0 ns