CHAPTER 1 PRODUCT SPECIFCATIONS
User's Manual A19069EJ2V0UM
42
1.7.6 SiP internal-connection DMA interface pins
(1) SBUSCLK-synchronization signal
The second DMA transfer request disable timing in single transfer is described below.
Table 1-18. SBUSCLK-synchronization Signal
Parameter Symbol
MIN.
MAX.
Unit
SDMARQZ0-SDMARQZ3 setup time (from SBUSCLK
↑
) t
SDRK
4.3
−
ns
SDMARQZ0-SDMARQZ3 hold time 1
t
HKDR1
To
DMAAKZ
↓
−
ns
SDMARQZ0-SDMARQZ3 hold time 2 (from SBUSCLK
↑
) t
HKDR2
−
4.3 m
×
t
BCLK
−
4.3
ns
SDMAAKZ0-SDMAAKZ3 output delay time (from SBUSCLK
↑
) t
DKDA
2.0 11.0
ns
SDMAAKZ0-SDMAAKZ3 low level width
t
WDAL
−
9.0
+
n
×
t
BCLK
9.0
+
n
×
t
BCLK
ns
STCZ0-STCZ3 output delay time (from SBUSCLK
↑
) t
DKTC
2.0 11.0
ns
Remarks 1.
t
BCLK
: SBUSCLK cycle
2.
m
=
0 to 15 (DMARQZ0 to DMARQZ3 signal mask widths set via DMAIFC0 to DMAIFC3 registers)
3.
n
=
1 to 16 (DMAAKZ0 to DMAAKZ3 signal active-level widths set via DMAIFC0 to DMAIFC3 registers)
Figure 1-21. DMA Interface (SBUSCLK-synchronization Signal)
SBUSCLK (output)
SDMARQZn (input)
SDMAAKZn (output)
< t
HKDR2
>
STCZn (output)
< t
DKTC
>
< t
DKDA
>
< t
WDAL
>
< t
HKDR1
>
< t
SDRK
>
Remark
n = 0, 1
