CHAPTER 1 PRODUCT SPECIFCATIONS
User's Manual A19069EJ2V0UM
17
(2) Output clock
Table 1-9. Output Clock Timing
Parameter Symbol
Conditions
MIN. MAX.
Unit
BUSCLK output cycle
t
BCYC
Output load capacitance: 30 pF and less
15
−
ns
BUSCLK high-level width
t
WKH1
0.5T
−
2.7 0.5T+2.7
ns
BUSCLK low-level width
t
WKL1
0.5T
−
2.7 0.5T+2.7
ns
BUSCLK rise time
t
KR1
3.3 ns
BUSCLK fall time
t
KF1
3.3 ns
SBUSCLK high-level width
t
WSKH1
0.5T
−
2.1 0.5T+2.1
ns
SBUSCLK low-level width
t
WSKL1
0.5T
−
2.1 0.5T+2.1
ns
SBUSCLK rise time
t
SKR1
1.85
ns
SBUSCLK fall time
t
SKF1
1.85
ns
VBCLKOUT output cycle
t
VCYC
Output load capacitance: 30 pF and less
10
−
ns
PLLFO output cycle
t
PLCYC
Output load capacitance: 20 pF and less
5
−
ns
Figure 1-1. Output Clock Timing
BUSCLK (output)
< t
BCYC
>
VBCLKOUT (output)
< t
VCYC
>
PLLFO (output)
< t
PLCYC
>
< t
WKH1
>
< t
WKL1
>
< t
KR1
>
< t
KF1
>
SBUSCLK (output)
< t
BCYC
>
< t
WSKH1
>
< t
WSKL1
>
< t
SKR1
>
< t
SKF1
>
<R>
