CHAPTER 1 PRODUCT SPECIFCATIONS
User's Manual A19069EJ2V0UM
38
(f) Page ROM access timing
Figure 1-18. Page ROM Access Timing
TASW
T1 TDW TW T2 TO1
TPRW
TW TO2
< t
HKW
>
< t
SKW
>
< t
HKW
>
< t
SKW
>
< t
DKA
>
< t
DKWRH
>
< t
DKRD H
>
< t
DKR DL
>
< t
HKID
>
< t
SKID
>
< t
DKBSL
>
< t
DKBSH
>
SBUSCLK (output)
SA0-SA20 (output)
SWRZ0-SWRZ1,
SWRSTBZ
(output)
SRDZ (output)
SD0-SD15
(I/O)
SWAITZ (input)
SBCYSTZ (output)
SCSZ0-SCSZ3
(output)
< t
DKA
>
< t
DKA
>
< t
DKA
>
< t
DKA
>
< t
DKRDH
>
< t
HKID
>
< t
SKID
>
< t
HKW
>
< t
SKW
>
< t
HKW
>
< t
SKW
>
Remarks 1.
Timing when the number of waits inserted by the DWC0 or DWC1 register is 0, the
number of idle states inserted by the BCC register is 1, and the number of waits inserted
by the ASC register is 1.
2.
Broken lines indicate high impedance.
