User's Manual A19069EJ2V0UM
9
LIST OF FIGURE
Figure No.
Title
Page
1-1 Output
Clock Timing ........................................................................................................................................17
1-2 Reset
Timing ...................................................................................................................................................18
1-3
Access Timing (SRAM, External ROM, External I/O) ......................................................................................20
1-4
Read Timing (SRAM, External ROM, External I/O) .........................................................................................21
1-5
Write Timing (SRAM, External ROM, External I/O)..........................................................................................22
1-6
DMA Flyby Transfer Timing (SRAM
→
External I/O) .......................................................................................23
1-7
DMA Flyby Transfer Timing (External I/O
→
SRAM Transfer) .........................................................................24
1-8 Page
ROM
Access Timing...............................................................................................................................25
1-9 Read
Timing
(SDRAM Access)........................................................................................................................27
1-10 Write
Timing
(SDRAM Access)........................................................................................................................28
1-11 Refresh
Timing (SDRAM Access)....................................................................................................................29
1-12 Bus
Hold Timing ..............................................................................................................................................31
1-13 Base
Access
Timing
(SRAM,
External ROM, External I/O) .............................................................................33
1-14
Read Timing (SRAM, External ROM, External I/O) .........................................................................................34
1-15
Write Timing (SRAM, External ROM, External I/O)..........................................................................................35
1-16
DMA Flyby Transfer Timing (SRAM
→
External I/O) .......................................................................................36
1-17
DMA Flyby Transfer Timing (External I/O
→
SRAM Transfer) .........................................................................37
1-18 Page
ROM
Access Timing...............................................................................................................................38
1-19 Bus
Hold Timing ..............................................................................................................................................40
1-20
DMA Interface (BUSCLK-synchronization Signal) ...........................................................................................41
1-21
DMA Interface (SBUSCLK-synchronization Signal).........................................................................................42
1-22
External Bus Reset Output Pin........................................................................................................................43
1-23 SiP
Internal-connection
Bus Reset Output Pin ................................................................................................43
1-24
CSI Access Timing (CKP, DAP
=
00) ...............................................................................................................45
1-25
CSI Access Timing (CKP, DAP
=
01) ...............................................................................................................45
1-26
CSI Access Timing (CKP, DAP
=
10) ...............................................................................................................46
1-27
CSI Access Timing (CKP, DAP
=
11) ...............................................................................................................46
1-28 Trace
Interface ................................................................................................................................................47
1-29 Debug
Serial Interface.....................................................................................................................................48
1-30 A/D
Converter
Characteristics .........................................................................................................................49
1-31 Equivalent
Circuit
of Analog Input Pins............................................................................................................49
2-1 SSCG-PLL
Block Diagram...............................................................................................................................51
