CHAPTER 2 INTERNAL SSCG-PLL CHARACTERISTICS
User's Manual A19069EJ2V0UM
52
2.2 Electrical Specifications
2.2.1 Recommended operating range
Parameter Symbol
Conditions MIN. MAX.
Unit
Oscillation Block Input Frequency
f
osc
−
2.0 50.0
MHz
Input Frequency
f
std
−
2.0 200.0
MHz
PFD Input Frequency
f
pfd
f
pfd
=
f
std
/ m
1.0
2.0
MHz
Input Duty
I
duty
−
30 70
%
Multiple Rate
MULT
MULT
=
n / m / p
0.182
50
−
m
−
2 128
−
n
−
93 100
−
Frequency Division Ratio Setting
p
−
1 4
−
2.2.2 Electrical specifications
Parameter Symbol
Conditions
MIN.
TYP
MAX
Unit
Remark
VCO Output Frequency
f
vco
f
vco
= f
std
×
n/m
100 200
MHz
Output Frequency
f
out
f
out
= f
std
×
n/m/p
25
200
MHz
Output Duty
duty
−
47 53
%
C
L
≤
0.2pF
Output Period Jitter
t
pj
−
−
150 150
Ps
Fixed
frequency mode
Multiple Rate
MULT
MULT = n/m/p
0.182
50
−
PLL13-PLL12(SSMDL1-SSMDL0)= 00
20
kHz
PLL13-PLL12(SSMDL1-SSMDL0)= 01
30
kHz
PLL13-PLL12(SSMDL1-SSMDL0)= 10
40
kHz
Modulation Period
f
mod
PLL13-PLL12(SSMDL1-SSMDL0)= 11
50
kHz
PLL16-PLL14(SSADJ2-SSADJ0)= 000
−
0.5 %
PLL16-PLL14(SSADJ2-SSADJ0)= 001
−
1.0 %
PLL16-PLL14(SSADJ2-SSADJ0)= 010
−
2.0 %
PLL16-PLL14(SSADJ2-SSADJ0)= 011
−
3.0 %
PLL16-PLL14(SSADJ2-SSADJ0)= 100
−
4.0 %
Frequency Modulation Rate f
dit
PLL16-PLL14(SSADJ2-SSADJ0)= 101
−
5.0 %
The settings are
performed without
modulation in the
setting conditions
other than those in
the left column.
Remark
The PFD input frequency is an output frequency of the M divider. Refer to
2.1 Block Diagram
.
