User's Manual A19069EJ2V0UM
10
LIST OF TABLES
Table No.
Title
Page
1-1 Terminology
for
Absolute Maximum Ratings ........................................................................................................ 11
1-2
Terminology for Recommended Operating Conditions......................................................................................... 11
1-3
Terminology for DC Characteristics ..................................................................................................................... 12
1-4 Absolute
Maximum Rating Values ....................................................................................................................... 13
1-5 Recommended
Operating Range ........................................................................................................................ 13
1-6
DC Characteristics (V
DD
= 3.3
±
0.3 V, T
A
= 0 to
+
70
°
C)...................................................................................... 14
1-7
Pull-up/Pull-down Resistance (V
DD
= 3.3
±
0.3 V, T
A
= 0 to +70
°
C) .................................................................... 15
1-8 Input
Clock Timing ............................................................................................................................................... 16
1-9 Output
Clock Timing ............................................................................................................................................ 17
1-10 Reset
Timing........................................................................................................................................................ 18
1-11
PFESiP/V850EP1 Maximum Operating Frequency on Operating Conditions...................................................... 19
1-12
Access Timing (SRAM, External ROM, External I/O)........................................................................................... 19
1-13 SDRAM
Access Timing........................................................................................................................................ 26
1-14 Bus
Hold Timing .................................................................................................................................................. 30
1-15
Access Timing (SRAM, External ROM, External I/O)........................................................................................... 32
1-16 Bus
Hold Timing .................................................................................................................................................. 39
1-17 BUSCLK-synchronization Signal ......................................................................................................................... 41
1-18 SBUSCLK-synchronization Signal ....................................................................................................................... 42
1-19
External Bus Reset Output Pin ............................................................................................................................ 43
1-20 SiP
Internal-connection Bus Interface Pin............................................................................................................ 43
1-21 CSI
Access
Timing (Master Mode) ...................................................................................................................... 44
1-22 CSI
Access
Timing (Slave Mode) ........................................................................................................................ 44
1-23 Trace
Interface..................................................................................................................................................... 47
1-24 Debug
Serial Interface ......................................................................................................................................... 48
1-25
A/D Converter Characteristics (EV
DD
= AV
DD
= AV
REFP
= 3.0 to 3.6 V, EV
SS
= AV
SS
= AV
REFM
= 0 V) ................... 49
1-26
Analog Input Pin Specifications ........................................................................................................................... 49
1-27
Capacitance of Interface Block (C
B
)..................................................................................................................... 50
1-28
Capacitance of Interface Block (Output Buffer/Bidirectional Buffer) (C
B
) ............................................................. 50
2-1 PLL
Operating Conditions.................................................................................................................................... 54
2-2
Setting SSCG-output Modulation Period by SSMDL0 to SSMDL1 ...................................................................... 55
2-3
Setting SSCG-output Frequency Modulation Rate .............................................................................................. 55
2-4 Setting
the
S-selector .......................................................................................................................................... 56
2-5
PLL FO Output Control by PLLFOEN Pin ............................................................................................................ 56
