Phytec phyCORE-LPC2292/94, Hardware Manual

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Memory Models
©
PHYTEC Messtechnik GmbH 2006 L-658e_5
51
optional 128kB On-Chip Non-Volatile Memory
0xF000 0000
0xFFFF FFFF
0xE000 0000
0x8000 0000
0x4000 1FFF
0x4000 0000
0x0004 0000
0x0002 0000
0x0000 0000
AHP Peripherals
VPB Peripherals
remapped Boot Block
Reserved
16kB On-Chip Static RAM
optional 128kB On-Chip Non-Volatile Memory
Up to 16MB ext. FLASH at /CS0
Up to 8MB ext. RAM at /CS1
optional Ethernet device at /CS2
0x8100 0000
0x8200 0000
0x8300 0000
free usable memory area at /CS3
0x8400 0000
Figure 8: phyCORE-LPC2292/94 Memory Model
The following formula is used to calculate the timing settings for any
access on the external asynchronous bus:
Standard read access : WST1 >= ((t
RAM
+ 20ns) / t
cyc
) – 2
Standart write access : WST2 >= ((t
WRITE
– tcyc +5 ns) / t
cyc
where t
cyc
= 1/ f
max
t
RAM
= memory acces time read of external memory
T
WRITE
= memory access time write of external memory