Phytec phyCORE-LPC2292/94 Hardware Manual Download Page 17

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Introduction

PHYTEC Messtechnik GmbH 2006 L-658e_5

•

up to 6 freely programmable Chip Select signals from on-board
CPLD device (requires changing the default CPLD code

•

one operating voltage for core & peripherals, 3.3 V, typ. < 280 mA
(with maximum circuitry installed at 60 MHz CPU frequency)

•

controller 1.8 V core voltage generated on-board

•

additional 5

V operating voltage for CAN transceivers,

typ. <12 mA

•

support of LPC2292/2294 single chip mode

•

support of ETM debug interface (only on debugCORE version)

Please contact PHYTEC if you have questions about changing the CPLD code.

Summary of Contents for phyCORE-LPC2292/94

Page 1: ...A product of a PHYTEC Technology Holding company phyCORE LPC2292 94 Hardware Manual Edition July 2006...

Page 2: ...YTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further res...

Page 3: ...J500 through J509 Ethernet Controller SMSC LAN91C111Configuration 33 3 13 J600 J601 J616 CAN Transceiver Configuration 36 3 14 J602 J603 J604 J605 CAN Interfaces 37 3 15 J606 Write Protection of SPI E...

Page 4: ...s and Jumpers 79 16 2 1 Connectors 79 16 2 2 Jumpers on the phyCORE Carrier Board HD200 81 16 2 3 Unsupported Features and Improper Jumper Settings 83 16 3 Functional Components on the phyCORE Carrier...

Page 5: ...Contents PHYTEC Messtechnik GmbH 2006 L 658e_5 17 Ethernet Port 121 18 Revision History 123 19 Component Placement Diagram 125 Index 127...

Page 6: ...ew 65 Figure 11 JTAG Interface Bottom View 66 Figure 12 debugCORE LPC2292 94 Top View 69 Figure 13 debugCORE LPC2292 94 Bottom View 70 Figure 14 Physical Dimensions 73 Figure 15 Modular Development an...

Page 7: ...9 Pin Assignment of the DB 9 Plug P2B CAN Transceiver on Carrier Board with Galvanic Separation 105 Figure 30 Pin Assignment Scheme of the Expansion Bus 109 Figure 31 Pin Assignment Scheme of the Patc...

Page 8: ...onfiguration 34 Table 17 J504 Ethernet LAN_IRQ Pull up Configuration 34 Table 18 J505 J506 J507 Ethernet EEPROM Configuration 34 Table 19 J508 Ethernet EEPROM Enable Configuration 35 Table 20 J509 Eth...

Page 9: ...ector at X500 72 Table 45 Improper Jumper Setting for JP30 33 on the Carrier Board 83 Table 46 JP9 JP16 Configuration of the Main Supply Voltages VCC VCC2 84 Table 47 JP9 JP16 Improper Jumper Settings...

Page 10: ...101 Table 63 Jumper Configuration for CAN Plug P2B using the CAN Transceiver on the Carrier Board HD200 102 Table 64 Improper Jumper Settings for the CAN Plug P2B CAN Transceiver on the Carrier Board...

Page 11: ...94 Carrier Board Expansion Board 115 Table 75 Pin Assignment Power Supply for the phyCORE LPC2292 94 Carrier Board Expansion Board 116 Table 76 Unused Pins on the phyCORE LPC2292 94 Carrier Board Exp...

Page 12: ...phyCORE LPC2292 94 PHYTEC Messtechnik GmbH 2006 L 658e_5...

Page 13: ...ic Conformity of the PHYTEC phyCORE LPC2292 94 PHYTEC Single Board Computers henceforth products are designed for installation in electrical appliances or as dedicated Evaluation Boards i e for use as...

Page 14: ...ould ensure conformance following any modifications to the products as well as implementation of the products into target systems The phyCORE LPC2292 94 is one of a series of PHYTEC Single Board Compu...

Page 15: ...approximately 20 of all pin header connectors on the phyCORE boards to Ground This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelin...

Page 16: ...ports extend to two 100 pin high density 0 635 mm Molex connectors aligning two sides of the board enabling it to be plugged like a big chip into target application 32 bit demultiplexed bus mode max...

Page 17: ...tage for core peripherals 3 3 V typ 280 mA with maximum circuitry installed at 60 MHz CPU frequency controller 1 8 V core voltage generated on board additional 5 V operating voltage for CAN transceive...

Page 18: ...I P S LPC2292 94 A0 A23 p h y C O R E C o n n e c t o r R S 2 3 2 A d d r F L A S H 2MB 16MB R A M 1MB 8MB D0 31 D a t a C A N RxD1 TxD1 RxD0 TxD0 CAN2H CAN2L SPI bus RxD0 TxD0 Reset E E P R O M CAN2...

Page 19: ...ik GmbH 2006 L 658e_5 7 1 2 View of the phyCORE LPC2292 94 PCM 023 L600 X701 RN200 U403 U301 U401 XT500 U303 U302 U606 X200 Q200 U605 XT200 U402 U201 U400 U600 U300 PL1231 1 PHYTEC 2 20 Figure 2 Top V...

Page 20: ...94 8 PHYTEC Messtechnik GmbH 2006 L 658e_5 1 RN500 U200 Q600 RN504 U601 U604 RN201 RN503 U501 U603 RN502 U607 RN700 U608 U602 U203 U500 RN501 U202 X700 RN600 19 RN601 D603 Figure 3 Bottom View of the...

Page 21: ...ed to as phyCORE connector This allows the phyCORE LPC2292 94 to be plugged into any target application like a big chip A new numbering scheme for the pins on the phyCORE connector has been introduced...

Page 22: ...extend to the bottom of the module The numbering scheme is thus consistent for both the module s phyCORE connector as well as mating connectors on the phyCORE Carrier Board or target hardware thereby...

Page 23: ...In order to facilitate understanding of the pin assignment scheme the diagram presents a crossview of the phyCORE module showing these phyCORE connectors mounted on the underside of the module s PCB F...

Page 24: ...native external interrupt 1 input 4A P020 I O Port 020 of the microcontroller see data sheet alternative external interrupt 3 input 5A CS0 O Chip Select 0 6A CS2 O Chip Select 2 8A WE O WR signal of t...

Page 25: ...f the microcontroller 33B BLS1 O Low active Byte Lane Select signal Bank1 35B FS1 I O Freely programmable PLD signal may be used as additional Chip Select signal 36B BLS3 O Low active Byte Lane Select...

Page 26: ...icrocontroller see data sheet 31C SCL I O I2 C clock line for RTC 33C LAN_LED_A O LINK LED output for Ethernet interface 34C LAN_LED_B O LAN LED output for Ethernet interface 35C LAN_TPI I Negative Rx...

Page 27: ...pulated 21D CAN_H1 I O Differential CANH line of the first CAN transceiver alternativ TD1 if J602 populated and U605 not populated 22D RxD0_ext I Input of the first serial interface RS 232 level 23D T...

Page 28: ...onal Chip Select signal 45D TDI_PLD I JTAG Scan Chain TDI signal from the PLD 46D TCK_PLD I JTAG Scan Chain TCK signal from the PLD 47D TDO_PLD O JTAG Scan Chain TDO signal from the PLD 44D 49D VAGND...

Page 29: ...jumpers are located at the top side microcontroller side of the module 1 2 e g J200 J201 e g J205 J206 1 3 2 2 1 4 3 e g J400 J401 Figure 5 Numbering of the Jumper Pads X701 J210 U403 J621 J617 J500 L...

Page 30: ...18 PHYTEC Messtechnik GmbH 2006 L 658e_5 RN500 J620 U200 RN601 Q600 RN504 U601 U604 RN201 RN503 U501 U603 RN502 U607 RN700 U608 J619 U203 U500 RN501 U202 X700 RN600 19 J622 Figure 7 Location of the J...

Page 31: ...U202 is not populated open2 CS0 of the controller connected with CPLD U202 CPLD generates CSF0 CSF1 signals J206 closed CS1 connected with CSR0 only if CPLD U202 is not populated open2 CS1 of the cont...

Page 32: ...pply via battery J500 1 2 EEPROM U500 ORG pin connected with VDD_V3V3 internal EEPROM organization configured to 16 2 3 EEPROM U500 ORG pin connected with GND internal EEPROM organization configured t...

Page 33: ...ected to GND See LAN91C111 data sheet for more details J508 open ENEEP signal on SMSC LAN 91C111 connected with internal pull up to VDD_V3V3 configuration via predefined EEPROM contents closed ENEEP s...

Page 34: ...as CAN TTL signal an X700D18 for connection to external CAN transceiver only in connection with unpopulated U606 J606 open SPI EEPROM not write protected closed SPI EEPROM write protected WP input tie...

Page 35: ...er available as standard I O pin at X700A50 open EEPROM MOSI0 signal not connected to the C on the module external connection required at pin X700C28 P06 is available as standard I O pin at X700A50 J6...

Page 36: ...M OCDS connector are supplied via VDD_V3V3 Configuration depends on Emulator requirements refer to applicable data sheets 2 3 Vsupply and VTREF are connected to GND Configuration depends on Emulator r...

Page 37: ...RxD0 and X700D23 TxD0 If the jumpers are opened the applicable controller pins P00 and P01 can be used with their alternative functions or the serial interface signals are available with their TTL le...

Page 38: ...reference voltage source VADVREF at X700D50 2 3 Default setting Table 5 J204 A D Converter Reference Voltage 3 4 J205 J206 Chip Select Configuration If the phyCORE LPC2292 94 is delivered with the mi...

Page 39: ...d these jumpers must be closed Table 6 J205 J206 Chip Select Configuration 3 5 J207 MCKO Signal This jumper can be used to connect the master clock output signal MCKO to Molex pin X700B1 for use in ex...

Page 40: ...CPLD reads the signal level on the applicable input pins and configures the individual Chip Select signals for the Flash devices accordingly Note Jumpers J208 and J209 are configured at time of deliv...

Page 41: ...eads the signal level on the applicable input pins and configures the individual Chip Select signals for the RAM devices accordingly Note Jumpers J210 and J211 are configured at time of delivery of th...

Page 42: ...per J300 Refer to the applicable Flash device Data Sheet User s Manual for more information about this feature The following configurations are possible Flash Ready Busy Configuration J300 Ready Busy...

Page 43: ...ices that could be populated on the module For more detailed information about the write protection function refer to the Data Sheet User s Manual of the Flash device in question The following configu...

Page 44: ...fast SRAMs BLS2 and BLS3 signals configured for accessing fast SRAMs i e 10 ns 1 2 3 4 1 2 3 4 BLS0 and BLS1 signals configured for accessing standard SRAMs BLS2 and BLS3 signals configured for acces...

Page 45: ...ontroller The LAN_IRQ signal can be connected to a 10k pull up resistor with the help of Jumper J504 Connection of the LAN91C111 controller s Ready LAN_RDY signal to port pin P018 is established by cl...

Page 46: ...3 closed Default setting Table 17 J504 Ethernet LAN_IRQ Pull up Configuration The LAN91C111 Ethernet controller provides 4 configuration inputs IOS0 IOS2 and ENEEP to enable access to the serial EEPRO...

Page 47: ...nable Configuration Jumper J509 configures the general purpose input port of the LAN91C111 Ethernet controller that is used to convey the LINK status EPHSR bit 14 This LINK_ON bit is typically used fo...

Page 48: ...transceiver U605 always active 1 2 don t care CAN transceiver U605 mode is controlled via port P020 on the LPC2292 94 microcontroller 2 3 don t care CAN transceiver U606 always active don t care 1 2 C...

Page 49: ...Supply Configuration 3 14 J602 J603 J604 J605 CAN Interfaces Two CAN interfaces are provided by the phyCORE LPC2292 94 The CAN signals extend to the two TLE6250V33 CAN transceivers at U605 and U606 T...

Page 50: ...ROM Various types of SPI EEPROM devices can populate space U607 Some of these devices provide a write protection function3 Closing Jumper J606 connects pin 3 of the serial EEPROM with GND and thus act...

Page 51: ...following configurations are possible Watchdog J607 MAX6301 configured for extended mode see IC data sheet for details WDS pin via pull up resistor disables watchdog due to floating WDI signal open A...

Page 52: ...pins P02 P03 P015 available as standard I O pins open open open Default setting Table 26 J608 J609 J610 I2 C Interface Configuration 3 18 J611 J612 J613 J614 SPI0 Interface Jumpers J611 through J614...

Page 53: ...cable CAN transceiver must be supplied with the required voltage level at pin 3 The following configurations are possible CAN Transceiver Supply Configuration J615 Pin 3 on CAN transceivers U605 and U...

Page 54: ...s are possible CAN Transceiver VCC Pin 5 J616 J617 Pin 5 on CAN transceivers U605 connected to 3 3 V supply voltage use only with TLE6250V33 devices closed Pin 5 on CAN transceivers U605 not connected...

Page 55: ...ed from VCC closed Default setting Table 30 J618 VDD_V3V3 Supply Control 3 22 J619 J620 SPI Master Slave Selection Jumpers J619 and J620 are used to configure the SPI interface mode If both jumpers re...

Page 56: ...is not controlled by the microcontroller if the WDT is used then the WDI signal needs to be controlled via Molex pin X700D8 open Microcontroller port P021 controls the WDI input signal Additional peri...

Page 57: ...0 and J801 are used to route certain signals to the ETM OCDS connector at X800 This connector is only available on the debugCORE LPC2292 94 Configuration of these jumpers greatly depends on the charac...

Page 58: ...val of the on board quartz oscillator and populating C210 with a 100p 50V capacitor Note Because of the oscillator properties C210 should not be closed when using the on board quartz oscillator This c...

Page 59: ...vel if the pin is left unconnected 4 7 k pull down resistors are recommended although the resistor value is also dependent upon the external circuitry connected to the port pins in question Table 36 a...

Page 60: ...rtup configuration with debugCORE LPC2292 94 4 2 Starting the LPC2292 94 ISP Mode In order to start the ISP command handler on the LPC2292 94 port P0 14 of the microcontroller must be connected to a l...

Page 61: ...banks installed on U300 U303 with either 1 MByte 2 MByte or 4 MByte devices in CBGA 48 packaging per shape The total amount of Flash memory is 2 MByte in the minimum configuration of the module and 16...

Page 62: ...le shows the predefined address ranges for the individual CS signals banks and the corresponding bus configuration registers Bank Address Range Configuration Register 0 8000 0000 80FF FFFF BCFG0 1 810...

Page 63: ...mory Up to 16MB ext FLASH at CS0 Up to 8MB ext RAM at CS1 optional Ethernet device at CS2 0x8100 0000 0x8200 0000 0x8300 0000 free usable memory area at CS3 0x8400 0000 Figure 8 phyCORE LPC2292 94 Mem...

Page 64: ...e 10 ns without PLD BCFG0 Register Configuration Value 0x02000 28A3 IDCY 3 4 idle cycle WST1 5 8 CCLK cycles RBLE 0 0 non byte partitioned device WST2 5 8 CCLK cycles BUSERR 0 not relevant WPERR 0 no...

Page 65: ...T2 5 8 CCLK cycles BUSERR 0 not relevant WPERR 0 no write protection error WP 0 bank not write protected BM 0 no burst ROM bank MW 2 32 bit wide bus AT 0 always write 0 to this field BCFG1 Register Co...

Page 66: ...ration Value 0x02000 0C23 IDCY 3 4 idle cycle WST1 1 4 CCLK cycles RBLE 1 byte partitioned device WST2 1 4 CCLK cycles BUSERR 0 not relevant WPERR 0 no write protection error WP 0 bank not write prote...

Page 67: ...line of the transceiver is connected to the TxD line of the COM port while the TxD line is connected to the RxD line of the COM port The Ground potential of the phyCORE LPC2292 94 circuitry needs to b...

Page 68: ...each end of the CAN bus For larger CAN bus systems an external opto coupler should be implemented to galvanically separate the CAN transceiver and the phyCORE LPC2292 94 This requires removal of the...

Page 69: ...sed at U607 at the time of printing of this manual Device Type Size Component Manufacturer EEPROM 1 kByte 1024 8 AT25080 Atmel EEPROM 2 kByte 2048 8 AT25160 Atmel EEPROM 4 kByte 4096 8 AT25320 Atmel E...

Page 70: ...age is required Use of a Flash device as the only code memory results in no or only a limited usability of the Flash memory as non volatile memory for data This is due to the internal structure of the...

Page 71: ...ide range of operating systems such as Linux etc U501 D0 D31 A2 A15 CS2 DATA ADDRESS CONTROL LPC229x 10 100Mbps ETHERNET U500 SPI_EEPROM phyCORE LPC229x External Figure 9 Ethernet Connection to LPC229...

Page 72: ...MAC Media Access Control address is a unique identification code of computer hardware operating within a LAN Local Area Network When connecting the hardware to the Internet the assigned IP number is m...

Page 73: ...been designed exclusively for operation in 10 100Base T networks The 10 100Base T interface with its signals LAN_LEDA and LAN_LEDB extends to phyCORE connector X1 The MII interface of the LAN91C111 is...

Page 74: ...94 is equipped with an internal I2 C controller the I2 C protocol is processed very effective without extensive processor action The Real Time Clock also provides an interrupt output that extends to t...

Page 75: ...cted to GND on the phyCORE LPC2292 94 As of the printing of this manual a lithium battery is recommended as it offers relatively high capacity at low discharge In the event of a power failure at VCC t...

Page 76: ...phyCORE LPC2292 94 64 PHYTEC Messtechnik GmbH 2006 L 658e_5...

Page 77: ...gram code into the external Flash or for debugging programs in the external SRAM The JTAG interface extends out to 2 mm pitch pin header rows X701 on the controller side of the module Figure 10 and Fi...

Page 78: ...side of the PCB The JTAG interface of the phyCORE LPC2292 94 can operate in various modes On board configuration resistors select if the corresponding port pins function as JTAG interface or as stand...

Page 79: ...nt Kits order code KPCM 023 JTAG connector X701 is not populated on phyCORE modules with order code PCM 014 that are intended for OEM implementation However all JTAG signals are also accessible at the...

Page 80: ...phyCORE LPC2292 94 68 PHYTEC Messtechnik GmbH 2006 L 658e_5...

Page 81: ...from its phyCORE counterpart in that an additional debug interface and corresponding circuitry has been added On the debugCORE LPC2292 94 there is also the possibility of connecting the MII interface...

Page 82: ...tch for configuration resistors R205 and R206 must be removed DIP switch S800 on the debugCORE LPC2292 94 has the following configuration options DIP Switch Open OFF Closed ON 1 Normal operation of th...

Page 83: ...onnected to VCC 3 3 V or GND via Jumper J801 default VCC 13 RTCK JTAG signal returned test clock output 14 Vsupply Can be connected to VCC 3 3 V or GND via Jumper J801 default VCC 15 TCK JTAG signal t...

Page 84: ...I PHY input 8 LAN_RXD0 Received data nibble from MII PHY input 9 LAN_RX_DV Envelope of data valid reception MII PHY input 10 LAN_RX_ER Code error detection by PHY input 11 LAN_RX25 Receive clock input...

Page 85: ...The module s profile is ca 7 2 mm thick with a maximum component height of 2 6 mm on the bottom connector side of the PCB and approximately 3 0 mm on the top microcontroller side The board itself is...

Page 86: ...Humidity 95 r F not condensed Operating voltage VCC 3 3 V 5 VCC2 5 V 5 VBAT 3 V 20 Power consumption VCC1 3 3 V 300 mA typical VCC2 5 0 V 12 mA typical Conditions VCC 3 3 V VBAT 0 V 2 MByte fast SRAM...

Page 87: ...100 k pull up resistor against VCC Removal of various components such as the microcontroller and the standard quartz is not advisable given the compact nature of the module Should this nonetheless be...

Page 88: ...phyCORE LPC2292 94 76 PHYTEC Me technik GmbH 2006 L 658e_5...

Page 89: ...mputer module The Carrier Board design allows easy connection of additional expansion boards featuring various functions that support fast and convenient prototyping and software evaluation This modul...

Page 90: ...and on board signals provided by the SBC module mounted on the Carrier Board are broken out 1 1 to the expansion board by means of its patch field 7 The required connections between SBC module Carrier...

Page 91: ...L6 R31 CB23 L5 R43 CB24 L4 R52 CB25 L3 R33 CB26 L2 L19 CB27 L10 X2 CB28 L1 X6 CB29 L18 X7 CB30 L17 X4 CB31 L16 X5 L15 U10 L14 S2 D10 L13 S1 D11 L12 U12 S_1 L11 U3 S_2 L9 U2 JP40 L20 U8 C36 C33 U11 R53...

Page 92: ...current Maximum signal input values are indicated in the corresponding controller User s Manual Data Sheets As damage from improper connections varies according to use and application it is the user...

Page 93: ...the phyCORE LPC2292 94 directly connects to the Reset button S2 Figure 17 illustrates the numbering of the jumper pads while Figure 18 indicates the location of the jumpers on the Carrier Board Figure...

Page 94: ...rier Board Jumper settings for other functional configurations of the phyCORE LPC2292 94 module mounted on the Carrier Board are described in section 16 3 JP30 JP14 JP15 X7 JP40 J1 J2 J3J4 JP41 JP28 J...

Page 95: ...does not support an RS 485 interface For this reason the corresponding jumper settings should never be used Jumper Setting Description JP30 closed TxD signal for second serial interface routed to pin...

Page 96: ...ly at X1 Caution Do not use a laboratory adapter to supply power to the Carrier Board Power spikes during power on could destroy the phyCORE module mounted on the Carrier Board Do not change modules o...

Page 97: ...6 open phyCORE LPC2292 94 not connected to secondary main supply voltage NOTE This setting is correct if the module in its minimum configuration without on board CAN transceivers is used Table 47 JP9...

Page 98: ...o the inactive state This is achieved by applying a high level signal at pin X700C9 BOOT of the phyCORE LPC2292 94 A transistor circuitry connects P0 14 to GND as long as the BOOT pin is high An on bo...

Page 99: ...P mode This spares pushing the Boot button during a hardware reset or power on Caution In this configuration a regular reset hence normal start of your application is not possible The microcontroller...

Page 100: ...s been removed In combination with Jumper JP41 left open a high level will be detected by the CPU at data line D26 which then causes instructions to be fetched from the controller internal Flash 2 Boo...

Page 101: ...yCORE LPC2292 94 JP21 open Pin 9 of DB 9 socket P1A not connected JP22 open Pin 7 of DB 9 socket P1A not connected JP23 open Pin 4 of DB 9 socket P1A not connected JP24 open Pin 6 of DB 9 socket P1A n...

Page 102: ...2292 94 JP23 1 2 Pin 4 of DB 9 socket P1A connected with MISO0 signal from phyCORE LPC2292 94 1 2 Pin 6 of DB 9 socket P1A connected with SCLK0 signal from phyCORE LPC2292 94 JP24 2 3 Pin 6 of DB 9 so...

Page 103: ...rnal devices connected to P1A This power supply option especially supports connectivity to analog and digital modems Such modem devices enable global communication of the phyCORE LPC2292 94 over the I...

Page 104: ...iting value that can be provided by the phyCORE Carrier Board HD200 the voltage at pin 6 will be switched off immediately This prevents damage to the phyCORE Carrier Board HD200 as well as connected m...

Page 105: ...hyCORE LPC2292 94 JP2 open Pin 9 of DB 9 socket P1B not connected JP3 open Pin 7 of DB 9 socket P1B not connected JP4 open Pin 4 of DB 9 socket P1B not connected JP5 open Pin 6 of DB 9 socket P1B not...

Page 106: ...connected with port P0 22 from phyCORE LPC2292 94 JP4 closed Pin 4 of DB 9 socket P1B connected with port PCS0 from phyCORE LPC2292 94 JP5 closed Pin 6 of DB 9 socket P1B connected with MOSI0 signal f...

Page 107: ...3 Pin 7 of the DB 9 plug P2A is connected to CAN_H1 from on board transceiver on the phyCORE module JP11 open Input at opto coupler U4 on the phyCORE Carrier Board HD200 open JP12 open Output at opto...

Page 108: ...o coupler U5 on the phyCORE Carrier Board HD200 connected with CAN_L1 RD1 of the phyCORE LPC2292 94 JP13 2 3 Supply voltage to CAN transceiver and opto coupler on the phyCORE Carrier Board HD200 JP18...

Page 109: ...er Board is connected to A22 of the phyCORE LPC2292 94 JP11 open Input at opto coupler U4 on the Carrier Board not connected 1 2 Output at opto coupler U5 on the Carrier Board is connected to MISO0 of...

Page 110: ...at opto coupler U4 on the Carrier Board connected to CAN_H1 TD1 of the phyCORE LPC2292 94 JP12 2 41 Output at opto coupler U5 on the Carrier Board connected to CAN_L1 RD1 of the phyCORE LPC2292 94 JP1...

Page 111: ...onfigured in order to routed the applicable voltage to the CAN voltage regulator at U8 on the Carrier Board VCAN_IN JP39 7 V 18 V 1 2 18 V 23 V 2 3 23 V 28 V open Table 60 JP39 CAN Bus Voltage Supply...

Page 112: ...hyCORE LPC2292 94 JP11 open Input at opto coupler U4 on the Carrier Board not connected 1 2 Output at opto coupler U5 on the Carrier Board is connected to MISO0 of the phyCORE LPC2292 94 2 3 Output at...

Page 113: ...n 7 of the DB 9 plug P2B is connected to CAN_H2 from on board transceiver on the phyCORE module JP14 open Input at opto coupler U6 on the phyCORE Carrier Board HD200 open JP15 open Output at opto coup...

Page 114: ...to coupler U7 on the Carrier Board connected to CAN_L2 RD2 of the phyCORE LPC2292 94 JP13 closed CAN transceiver and opto coupler on the Carrier Board connected with 5 V supply voltage JP18 closed GND...

Page 115: ...U6 on the Carrier Board is connected to P1 21 of the phyCORE LPC2292 94 2 3 Input at opto coupler U6 on the Carrier Board is connected to A23 of the phyCORE LPC2292 94 JP14 open Input at opto coupler...

Page 116: ...at opto coupler U6 on the Carrier Board connected to CAN_H2 TD2 of the phyCORE LPC2292 94 JP15 2 41 Output at opto coupler U7 on the Carrier Board connected to CAN_L2 RD2 of the phyCORE LPC2292 94 JP1...

Page 117: ...esstechnik GmbH 2006 L 658e_5 105 Pin 9 VCAN Pin 3 VCAN Pin 7 CAN H1 galvanically separated Pin 2 CAN L1 galvanically separated Pin 6 VCAN Figure 29 Pin Assignment of the DB 9 Plug P2B CAN Transceiver...

Page 118: ...94 2 3 Input at opto coupler U6 on the Carrier Board is connected to A23 of the phyCORE LPC2292 94 JP14 open Input at opto coupler U6 on the Carrier Board not connected 1 2 Output at opto coupler U7...

Page 119: ...f the Programmable LED D3 16 3 10 User Push Button S3 The phyCORE Carrier Board HD200 starting with PCB revision 1179 6 offers a push button at S3 for user implementations Jumper JP40 connects this pu...

Page 120: ...nsion board that mounts to the Carrier Board at X2 Please note that depending on the design and size of the expansion board only a portion of the entire patch field is utilized under certain circumsta...

Page 121: ...ver the numbering scheme for Expansion Bus connector and patch field matrices differs from that of the phyCORE connector as shown in the following two figures B A D C 80 1 80 1 Figure 30 Pin Assignmen...

Page 122: ...D4 21A 21A 34D D5 21B 21B 34F D6 22B 22B 35A D7 23A 23A 35E D8 28B 28B 37C D9 29A 29A 37E D10 30A 30A 37B D11 30B 30B 37F D12 31A 31A 38A D13 31B 31B 38C D14 32B 32B 38E D15 33A 33A 38B D16 37B 37B 40...

Page 123: ...1A 11A 31E A5 11B 11B 31B A6 12B 12B 31F A7 13A 13A 32A A8 13B 13B 32C A9 14A 14A 32E A10 15A 15A 32B A11 15B 15B 32F A12 16A 16A 33A A13 16B 16B 33C A14 17B 17B 33E A15 18A 18A 33B A16 23B 23B 35B A1...

Page 124: ...A 35A 39E FS1 35B 35B 39B FS2 11C 11C 4E FS3 43D 43D 15A FS4 44C 44C 15C FS5 45C 45C 15E BLS0 34A 34A 39A BLS1 33B 33B 38F BLS2 36A 36A 39D BLS3 36B 36B 39F OE 7B 7B 30A WE 8A 8A 30E RESIN 10D 10D 3F...

Page 125: ...3D 13D 5A P012 14C 14C 5C P013 15C 15C 5E P014 IRQ1 3A 3A 28B P015 IRQ2 3B 3B 28F P016 IRQ0 2B 2B 28E P017 15D 15D 5B P018 16C 16C 5F P019 19C 19C 6F P020 4A 4A 29A P021 24C 24C 8B P022 25C 25C 8D P02...

Page 126: ...KT3 30C 30C 10E P1 20 TRACESYNC 30D 30D 10B P1 21 PIPESTAT0 31D 31D 11A P1 22 PIPESTAT1 41C 41C 14A P1 23 PIPESTAT2 41D 41D 14E P1 24 TRACECLK 42D 42D 14B P1 25 EXTIN0 43C 43C 14F P1 26 RTCK 37D 37D 1...

Page 127: ...B MOSI0 28C 28C 9F PCS0 26C 26C 9A LAN_LED_A 33C 33C 11E LAN_LED_B 34C 34C 11F LAN_TPI 35C 35C 12A LAN_TPI 35D 35D 12E LAN_TPO 36C 36C 12B LAN_TPO 36D 36D 12D RTCK P126 37D 37D 12F TDO P127 38D 38D 12...

Page 128: ...14D 19D 24D 29D 34D 39D 2A 7A 12A 17A 22A 27A 32A 37A 42A 47A 52A 57A 62A 67A 72A 77A 4B 9B 14B 19B 24B 29B 34B 39B 44B 49B 54B 59B 64B 69B 74B 79B 3C 7C 12C 17C 22C 27C 32C 37C 42C 47C 52C 57C 62C 67...

Page 129: ...C 73C 74C 75C 76C 78C 79C 80C 4D 5D 7D 8D 51D 53D 54D 55D 56D 58D 59D 60D 61D 63D 64D 65D 66D 68D 69D 70D 71D 73D 74D 75D 76D 78D 79D 80D 18A 19A 20A 21A 22A 23A 24A 25A 26A 27A 45A 46A 47A 48A 49A 50...

Page 130: ...s responsibility to ensure sufficient SRAM power supply during runtime The optional battery required for the RTC buffering refer to section 10 is available through PHYTEC order code BL 011 16 3 13 DS...

Page 131: ...al Number 16 3 14 Pin Header Connector X4 The pin header X4 on the Carrier Board enables connection of an optional modem power supply Connector X4 supplies 5 V at pin 1 and provides the phyCORE Carrie...

Page 132: ...phyCORE LPC2292 94 120 PHYTEC Me technik GmbH 2006 L 658e_5...

Page 133: ...et controller mounted on a Carrier Board HD200 to a 10 100Base T network1 Figure 34 Ethernet Transformer Module Connector The pinout for the Ethernet transformer connector is shown below Pin Function...

Page 134: ...will route the signals to Ethernet interface connector X7 Changing this jumper default configuration allows use of the signals on the Expansion Bus in combination with a phyCORE module lacking the Eth...

Page 135: ...PCM 997 V2 PCB 1179 5 Section 4 2 Starting the LPC2292 94 ISP Mode added In section 13 debugCORE LPC2292 94 3 25 ETM OCDS Connector at X800 and 3 12 LAN MII Connector at X500 pinout added Section 16...

Page 136: ...phyCORE LPC2292 94 124 PHYTEC Me technik GmbH 2006 L 658e_5...

Page 137: ...632 J618 R300 J205 CB711 CB613 J209 C604 R203 CB722 R209 R612 C204 J615 X200 J606 U201 R303 CB731 CB733 J208 CB713 C500 J300 Q200 J609 C208 J211 U600 CB723 R206 J204 CB730 XT200 R208 D602 CB712 U403 J...

Page 138: ...X700 CB710 C607 CB616 R507 CB610 R622 R212 U200 U602 U603 R609 C202 RN502 CB611 CB621 CB615 C201 RN504 C606 J619 C212 R607 U500 R614 R604 R621 Q600 R615 RN201 J620 Q601 U601 C203 RN503 R502 U604 R611...

Page 139: ...f the Carrier Board 77 Connector X4 119 CPLD 28 29 D Debug Interface 65 debugCORE LPC2292 94 69 Dimensions 74 DS2401 118 E EEPROM Serial 57 EEPROM Write Protection 38 EMC 1 Emulator 67 Ethernet 59 Eth...

Page 140: ...J605 37 J606 38 J607 39 J608 40 J609 40 J610 40 J611 40 J612 40 J613 40 J614 40 J615 41 J616 36 42 J617 42 J618 43 J619 43 J620 43 J621 44 J622 44 J800 45 J801 45 JA 002 67 JP17 107 JP19 118 JP40 107...

Page 141: ...d Serial Interface 93 Serial Interface 1 25 Serial Interface 2 24 Serial Interfaces 55 Silicon Serial Number 118 SMSC LAN91C111 33 SMT Connector 9 Socket P1A First RS 232 89 Socket P1B Second RS 232 9...

Page 142: ...phyCORE LPC2292 94 130 PHYTEC Me technik GmbH 2006 L 658e_5...

Page 143: ...ORE LPC2292 94 Document number L 658e_5 July 2006 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC Tec...

Page 144: ...Published by PHYTEC Me technik GmbH 2006 Ordering No L 658e_5 Printed in Germany...

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