Phytec phyCORE-LPC2292/94, Hardware Manual

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phyCORE-LPC2292/94
72
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PHYTEC Meßtechnik GmbH 2006 L-658e_5
The pinout of the 24-pin MII (0.64 mm pitch) connector at X500 is
described below:
Pin Number Signal Description
1, 20, 21 VCC 3.3 V supply voltage
2 LAN_MDI MII management data input
3 LAN_MDO MII management data output
4 LAN_MCLK MII management clock
5 LAN_RXD3 Received data nibble from MII PHY, input
6 LAN_RXD2 Received data nibble from MII PHY, input
7 LAN_RXD1 Received data nibble from MII PHY, input
8 LAN_RXD0 Received data nibble from MII PHY, input
9 LAN_RX_DV Envelope of data valid reception, MII PHY
input
10 LAN_RX_ER Code error detection by PHY input
11 LAN_RX25 Receive clock input from MII PHY
12 LAN_TX25 Transmit clock input from MII PHY
13 LAN_TXEN Output to MII PHY
14 LAN_TXD0 Transmit data nibble to MII PHY, output
15 LAN_TXD1 Transmit data nibble to MII PHY, output
16 LAN_TXD2 Transmit data nibble to MII PHY, output
17 LAN_TXD3 Transmit data nibble to MII PHY, output
18 LAN_COL Collision detect input from MII PHY.
19 LAN_CRS Envelope of packet reception from MII PHY.
22, 23, 24 GND Ground
Table 44: LAN MII Connector at X500