Phytec phyCORE-LPC2292/94, Hardware Manual

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Pin Description
©
PHYTEC Messtechnik GmbH 2006 L-658e_5
13
Pin Number Signal I/O Description
Pin Row X700B
1B MCKO O CLKOUT system clock output (only available if
Jumper J207 is populated)
2B P016 I/O Port 016 of the microcontroller (see data sheet)
(alternative: external interrupt 0 input)
3B P015 I/O Port 015 of the microcontroller (see data sheet)
(alternative: external interrupt 2 input)
4B, 9B, 14B, 19B,
24B, 29B, 34B,
39B, 44B, 49B
GND - Ground
5B /CS1 O Chip Select #1
6B /CS3 O Chip Select #3
7B /OE O Output enable signal of the microcontroller
8B, 10B, 11B,
12B, 13B, 15B,
16B, 17B,
23B, 25B,
26B, 27B
A0, A3, A5,
A6, A8, A11,
A13, A14,
A16, A19,
A21, A22 O Address line of the microcontroller
18B, 20B, 21B,
22B, 28B, 30B,
31B, 32B, 37B,
38B, 40B, 41B,
42B, 43B, 45B,
46B
D0, D3, D5,
D6, D8, D11,
D13, D14, D16,
D18, D21, D23,
D24, D26, D29,
D31 I/O Data line of the microcontroller
33B /BLS1 O Low active Byte Lane Select signal (Bank1)
35B FS1 I/O Freely programmable PLD signal (may be used as
additional Chip Select signal)
36B /BLS3 O Low active Byte Lane Select signal (Bank3)
47B, 48B,
50B
P02, P04,
P07 I/O Port 0 of the microcontroller
( see corresponding Data Sheet )
Pin Row X700C
1C, 2C VCC - Voltage input +3.3 VDC
3C, 7C, 12C, 17C,
22C, 27C, 32C,
37C
GND - Ground 0 V
4C, 5C VDD_V5V0 - Voltage input +5 VDC
6C VBAT I Battery input for back-up of RTC and optional
buffering of RAM
8C N.C. - Not connected
9C BOOT I Boot input of the phyCORE module, switches
controller into boot mode during reset
10C /RESET O /RESET output of the phyCORE-LPC2292/94
11C FS2 I/O Freely programmable PLD signal (may be used as
additional Chip Select signal)
13C P010 I/O Port P010 of the microcontroller (see data sheet)
14C P012 I/O Port P012 of the microcontroller (see data sheet)
15C P013 I/O Port P013 of the microcontroller (see data sheet)
16C P018 I/O Port P018 of the microcontroller (see data sheet)